TMS320TCI6489 Datasheet, PDF (45/197 Pages) Texas Instruments – TMS320TCI6489 Communications Infrastructure Digital Signal Processor

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TMS320TCI6489
SPRS626B – NOVEMBER 2009 – REVISED APRIL 2011
3.3 Device State Control Registers
The TCI6489 device has a set of registers that are used to control the status of its peripherals. These
registers are shown in Table 3-2.
Table 3-2. Device State Control Registers
ADDRESS START ADDRESS END
0288 0800
0288 0803
0288 0804
0288 0807
0288 0808
0288 080C
0288 0810
0288 0814
0288 080B
0288 080F
0288 0813
0288 0817
SIZE
4B
4B
4B
4B
4B
4B
0288 0818
0288 0828
0288 082C
0288 0830
0288 0834
0288 083C
0288 0840
0288 0900
0288 0904
0288 0908
0288 090C
0288 0940
0288 0944
0288 0948
0288 0827
0288 082B
0288 082F
0288 0833
0288 083B
0288 083F
0288 08FF
0288 0903
0288 0907
0288 090B
0288 093F
0288 0943
0288 0947
0288 094B
16B
4B
4B
4B
8B
4B
192B
4B
4B
4B
52B
4B
4B
4B
ACRONYM
DEVCFG1
DEVSTAT
DSP_BOOT_ADDR0
DSP_BOOT_ADDR1
DSP_BOOT_ADDR2
DEVID
Reserved
Reserved
Reserved
Reserved
EFUSE_MAC
PRI_ALLOC
Reserved
IPCGR0
IPCGR1
IPCGR2
Reserved
IPCAR0
IPCAR1
IPCAR2
DESCRIPTION
The first register with the parameters is set through
software to configure different components on the device
Stores all parameters latched from configuration pins or
configured through the DEVCFG register
The boot address for C64x+ Megamodule Core 0
The boot address for C64x+ Megamodule Core 1
The boot address for C64x+ Megamodule Core 2
Parameters for DSP device IDs also referred to as JTAG
or BSDL IDs. These must be readable by the
configuration bus so that this can be accessed via JTAG
and CPU
Required for EMAC boot
Priority Allocation Register
N/A
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
N/A
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
Register provided to facilitate inter-DSP interrupts and
utilized by hosts or C64x+ Megamodules to generate
interrupts to other DSPs
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Device Configuration
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