TMS320TCI6489 Datasheet, PDF (1/197 Pages) Texas Instruments – TMS320TCI6489 Communications Infrastructure Digital Signal Processor

TMS320TCI6489
www.ti.com
SPRS626B – NOVEMBER 2009 – REVISED APRIL 2011
TMS320TCI6489 Communications Infrastructure Digital Signal Processor
1 Features
12
• Key Features
– High-Performance Communications
Infrastructure DSP (TCI6489)
– 1.18-ns Instruction Cycle Time
– 850-MHz Clock Rate
– 0°C to 100°C Commercial Temperature
– 3 TMS320C64x+™ DSP Cores; Six RSAs for
CDMA Processing (2 per core)
– One Receive Accelerator (RAC)
– Enhanced VCP2/TCP2
– Frame Synchronization Interface
– 16-/32-Bit DDR2-667 Memory Controller
– EDMA3 Controller
– Antenna Interface
– One 1.8-V Inter-Integrated Circuit (I2C) Bus
– Two 1.8-V McBSPs
– 1000 Mbps Ethernet MAC (EMAC)
– Six 64-Bit General-Purpose Timers
– 16 General-Purpose I/O (GPIO) Pins
– Internal Semaphore Module
– System PLL and PLL Controller/DDR PLL
and PLL Controller, Dedicated to DDR2
Memory Controller
• High-Performance Communications
Infrastructure DSP (TCI6489)
– 1.18-ns Instruction Cycle Time
– 850-MHz Clock Rate
– Eight 32-Bit Instructions/Cycle
– 0°C to 100°C Commercial Temperature
• 3 TMS320C64x+™ DSP Cores
– Dedicated SPLOOP Instructions
– Compact Instructions (16-Bit)
– Exception Handling
• TMS320C64x+ Megamodule L1/L2 Memory
Architecture
– 256 K-Bit (32 K-Byte) L1P Program Cache
[Direct Mapped]
– 256 K-Bit (32 K-Byte) L1D Data Cache
[2-Way Set-Associative]
– 24 M-Bit (3072 K-Byte) Total L2 Unified
Mapped RAM/Cache
– 512 K-Bit (64 K-Byte) L3 ROM
• One Receive Accelerator (RAC)
– Performs Chip-Rate RX Functions
– Up to 64 Macro-BTS Users
– Up to 160 km cell size
• Six RSAs for CDMA Processing (2 per core)
– Dedicated RAKE, PATH_SEARCH and
RACH_SEARCH Instructions
– Transmit Processing Capability
• Enhanced VCP2
– Supports Over 694 7.95-Kbps AMR
• Enhanced Turbo Decoder Coprocessor (TCP2)
– Supports up to Eight 2-Mbps 3 GPP
(6 Iterations)
• Endianness: Little Endian, Big Endian
• Frame Synchronization Interface
– Time Alignment Between Internal
Subsystems, External Devices/System
– OBSAI RP1 Compliant for Frame Burst Data
– Alternate Interfaces for non-RP1 and
non-UMTS Systems
• 16-/32-Bit DDR2-667 Memory Controller
• EDMA3 Controller (64 Independent Channels)
• Antenna Interface
– 4 Configurable Links (Full Duplex)
– Supports OBSAI RP3 Protocol, v1.0:
768-Mbps, 1.536-, 3.072-Gbps Link Rates
– Supports CPRI Protocol V2.0: 614.4-Mbps,
1.2288-, 2.4576-Gbps Link Rates
– Clock Input Independent or Shared with CPU
(Selectable at Boot-Time)
• One 1.8-V Inter-Integrated Circuit (I2C) Bus
• Two 1.8-V McBSPs
• 1000 Mbps Ethernet MAC (EMAC)
– IEEE 802.3 Compliant
– Supports SGMII, v1.8 Compliant
– 8 Independent Transmit (TX) and 8
Independent Receive (RX) Channels
• Six 64-Bit General-Purpose Timers
– Configurable up to Twelve 32-Bit Timers
– Configurable in a Watchdog Timer mode
• 16 General-Purpose I/O (GPIO) Pins
• Internal Semaphore Module
– Software Method to Control Access to
Shared Resources
– 32 General Purpose Semaphore Resources
• System PLL and PLL Controller
• DDR PLL and PLL Controller, Dedicated to
1
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