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TMS320F28335_13 Datasheet, PDF (43/199 Pages) Texas Instruments – Digital Signal Controllers (DSCs)
TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
www.ti.com
SPRS439M – JUNE 2007 – REVISED AUGUST 2012
3.2.8 L0, L1, L2, L3, L4, L5, L6, L7 SARAMs
The F28335/F28235 and F28334/F28234 each contain 32K × 16 of single-access RAM, divided into
8 blocks (L0–L7 with 4K each). The F28332/F28232 contain 24K × 16 of single-access RAM, divided into
6 blocks (L0–L5 with 4K each). Each block can be independently accessed to minimize CPU pipeline
stalls. Each block is mapped to both program and data space. L4, L5, L6, and L7 are DMA-accessible.
3.2.9 Boot ROM
The Boot ROM is factory-programmed with boot-loading software. Boot-mode signals are provided to tell
the bootloader software what boot mode to use on power up. The user can select to boot normally or to
download new software from an external connection or to select boot software that is programmed in the
internal Flash/ROM. The Boot ROM also contains standard tables, such as SIN/COS waveforms, for use
in math related algorithms.
Table 3-6. Boot Mode Selection
MODE
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
GPIO87/XA15
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
GPIO86/XA14
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
(1) All four GPIO pins have an internal pullup.
GPIO85/XA13
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
GPIO84/XA12
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
MODE (1)
Jump to Flash
SCI-A boot
SPI-A boot
I2C-A boot
eCAN-A boot
McBSP-A boot
Jump to XINTF x16
Jump to XINTF x32
Jump to OTP
Parallel GPIO I/O boot
Parallel XINTF boot
Jump to SARAM
Branch to check boot mode
Branch to Flash, skip ADC calibration
Branch to SARAM, skip ADC
calibration
Branch to SCI, skip ADC calibration
NOTE
Modes 0, 1, and 2 in Table 3-6 are for TI debug only. Skipping the ADC calibration function
in an application will cause the ADC to operate outside of the stated specifications
Copyright © 2007–2012, Texas Instruments Incorporated
Functional Overview
43
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TMS320F28232