TMS320F28335_13 Datasheet, PDF (167/199 Pages) Texas Instruments – Digital Signal Controllers (DSCs)

TMS320F28335, TMS320F28334, TMS320F28332
TMS320F28235, TMS320F28234, TMS320F28232
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SPRS439M – JUNE 2007 – REVISED AUGUST 2012
Table 6-48. XHOLD/XHOLDA Timing Requirements (XCLKOUT = XTIMCLK) ^{(1) (2)}
MIN
MAX UNIT
t_d(HL-HiZ)
t_d(HL-HAL)
t_d(HH-HAH)
t_d(HH-BV)
t_d(HL-HAL)
Delay time, XHOLD low to Hi-Z on all address, data, and control
Delay time, XHOLD low to XHOLDA low
Delay time, XHOLD high to XHOLDA high
Delay time, XHOLD high to bus valid
Delay time, XHOLD low to XHOLDA low
4t_c(XTIM) + 30
ns
5t_c(XTIM) + 30
ns
3t_c(XTIM) + 30
ns
4t_c(XTIM) + 30
ns
4t_c(XTIM) + 2t_c(XCO) + 30
ns
(1) When a low signal is detected on XHOLD, all pending XINTF accesses will be completed before the bus is placed in a high-impedance
state.
(2) The state of XHOLD is latched on the rising edge of XTIMCLK.
XCLKOUT
(/1 Mode)
XHOLD
XHOLDA
XR/W
XZCS0, XZCS6, XZCS7
t_d(HL-Hiz)
t_d(HL-HAL)
t_d(HH-HAH)
t_d(HH-BV)
High-Impedance
XA[19:0]
Valid
High-Impedance
XD[31:0], XD[15:0]
Valid
(A)
A. All pending XINTF accesses are completed.
B. Normal XINTF operation resumes.
Figure 6-29. External Interface Hold Waveform
Valid
(B)
Copyright © 2007–2012, Texas Instruments Incorporated
Electrical Specifications 167
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