PGA411-Q1 Datasheet, PDF (42/105 Pages) Texas Instruments – Resolver Sensor Interface

PGA411-Q1
SLASE76D – NOVEMBER 2015 – REVISED APRIL 2016
Table 3. PGA411-Q1 Fault Reporting Summary (continued)
FAULT DESCRIPTION
Configuration and control registers CRC fault
User EEPROM space CRC fault
Trim EEPROM space CRC fault
SPI communication fault
Analog BIST fault
Logic BIST fault
Oscillator fault
FAULT pin read-back missmatch error
SPI FAULT BIT
FRCRC
FCECRC
FTECRC
SPI_ERR
ABISTF
LBISTF
(RESET state)
IOFAULT
FAULT PIN MASK FAULT PIN
BIT
STATE
EXCITER
OUTPUT
Off
On
Hi-Z / High
Low
—
Off ⁽¹⁾
Off
Off ⁽¹⁾
www.ti.com
EXCITER
OVERRIDE
ENBISTF
ENIOFAULT
7.4 Device Functional Modes
The PGA411-Q1 device implements a digital state machine that is responsible for device functional operation,
decision making, and system monitoring. See Figure 2 shows a detailed timing diagram of device power up.
When the SPI is active the current device-operating state is found by reading the DEVSTATE bits in the
DEV_STAT7 register.
~NRESET |
Oscillator_Fault |
Thermal_Shutdown |
VDD Under_Voltage |
VCC Under_Voltage
RESET⁽²⁾
FAULT = 0
Boost = OFF
Exciter = OFF
DTL = OFF
NRESET
[~ABISTF & ~LBISTF &
~FAFECAL] |
[63, : ',$*(;,7 = 1]
DIAGNOSTICS
NORMAL
FAULT = 0
Boost = OFF
Exciter = OFF⁽³⁾
DTL = OFF⁽³⁾
FAULT = 0
Boost = ON
Exciter = ON/OFF⁽¹⁾
DTL = ON
[63, : 63,',$* = 1]
fault_list
FAULTRES
FAULT
FAULT = Hi-Z/High
Boost = ON
Exciter = ON/OFF⁽¹⁾
DTL = OFF
Symbol Legend:
~ Logical NOT
& Logical AND
| Logical OR
: SPI Value change
Internal Signal
Device Pin
” Boost refers to the Exciter Power Supply (Boost Regulator).
” Exciter refers to the Exciter Signal Power Amplifier.
” DTL refers to the integrated Digital Tracking Loop.
fault_list:
[EXTMODE = 00 | EXTMODE = 11] |
[EXTOV & ~MEXTOV] |
[EXTUV & ~MEXTUV] |
[(FEXTMONH | FEXTMONL) & ~MEXTMON] |
[FIZHx & ~MIZOVx] |
[FIZLx & ~MIZUVx] |
[FOSHORT & ~MFOSHORT] |
[FOSINOPH & ~MFOSINOPH] |
[FOCOSOPH & ~MFOCOSOPH] |
[FOSINOPL & ~MFOSINOPL] |
[FOCOSOPL & ~MFOCOSOPL] |
[FLOOPE & ~ MFLOOPE] |
FBSTOV |
FVCCOV |
FVDDOV |
FVDDOC |
FTSD2 |
FGOPEN |
FRCRC |
FCECRC |
FTECRC |
SPI_ERR |
ABISTF |
LBISTF
(1) Depends on Exciter Override selection, behavior implementation, or both as listed in Table 3.
(2) Not a physical state. When the device is in the RESET state, an nPOR signal is asserted to digital logic.
(3) Setting the EXTEN bit to 1 enables the exciter amplifier. Setting the LPEN bit to 1 enables the digital tracking loop.
Figure 37. State Diagram
7.4.1 PGA411-Q1 Reset
The RESET state is not a physical state-machine controller state. The RESET state in Figure 37 signifies an
nPOR asserted in the PGA411-Q1 device, forcing the digital logic into reset (digital is frozen). On nPOR release
the digital logic begins operating from the DIAGNOSTICS state.
In the system, the NRESET pin asserts the nPOR in the device logic. When the NRESET pin is low (DGND), the
PGA411-Q1 logic is frozen and the device is in the RESET state. When the NRESET pin is pulled up, the logic is
enabled after a 70-µs deglitch period and the device is operational.
In the RESET state, all functional blocks inside the PGA411-Q1 device are disabled, including the exciter boost
regulator, exciter output amplifier, digital tracking loop, AFE, V_DD regulator, and oscillator. The state of the FAULT
pin is low.
42
Submit Documentation Feedback
Product Folder Links: PGA411-Q1
Copyright © 2015–2016, Texas Instruments Incorporated