ADC081500 Datasheet, PDF(42/47 Page) National Semiconductor (TI) – High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter

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ADC081500 Datasheet, PDF (42/47 Pages) National Semiconductor (TI) – High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter

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ADC081500

SNAS319G â JUNE 2005 â REVISED APRIL 2013

Table 10. Extended Control Mode Operation

(Pin 14 Floating)

Function

SCLK (Serial Clock)

SDATA (Serial Data)

127

SCS (Serial Interface Chip Select)

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COMMON APPLICATION PITFALLS

Failure to write all register locations when using extended control mode. When using the serial interface, all

3 user registers must be written at least once with the default or desired values before calibration and

subsequent use of the ADC. Once all registers have been written once, other desired settings can be loaded.

Driving the inputs (analog or digital) beyond the power supply rails.For device reliability, no input should go

more than 150 mV below the ground pins or 150 mV above the supply pins. Exceeding these limits on even a

transient basis may not only cause faulty or erratic operation, but may impair device reliability. It is not

uncommon for high speed digital circuits to exhibit undershoot that goes more than a volt below ground.

Controlling the impedance of high speed lines and terminating these lines in their characteristic impedance

should control overshoot.

Care should be taken not to overdrive the inputs of the ADC081500. Such practice may lead to conversion

inaccuracies and even to device damage.

Incorrect analog input common mode voltage in the d.c. coupled mode. As discussed in THE ANALOG

INPUT and D.C. Coupled Input, the Input common mode voltage must remain within 50 mV of the VCMO output,

which has a variability with temperature that must also be tracked. Distortion performance will be degraded if the

input common mode voltage is more than 50 mV from VCMO .

Using an inadequate amplifier to drive the analog input. Use care when choosing a high frequency amplifier

to drive the ADC081500 as many high speed amplifiers will have higher distortion than will the ADC081500,

resulting in overall system performance degradation.

Driving the VBG pin to change the reference voltage. As mentioned in THE REFERENCE VOLTAGE, the

reference voltage is intended to be fixed by FSR pin or Full-Scale Voltage Adjust register settings. Over driving

this pin will not change the full scale value, but can otherwise upset operation.

Driving the clock input with an excessively high level signal. The ADC input clock level should not exceed

the level described in the Operating Ratings Table or the input offset could change.

Inadequate input clock levels. As described in THE CLOCK INPUTS, insufficient input clock levels can result in

poor performance. Excessive input clock levels could result in the introduction of an input offset.

Using a clock source with excessive jitter, using an excessively long input clock signal trace, or having

other signals coupled to the input clock signal trace. This will cause the sampling interval to vary, causing

excessive output noise and a reduction in SNR performance.

Failure to provide adequate heat removal. As described in Thermal Management, it is important to provide

adequate heat removal to ensure device reliability. This can be done either with adequate air flow or the use of a

simple heat sink built into the board. The backside pad should be grounded for best performance.

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