ADC081500 Datasheet, PDF (31/47 Pages) National Semiconductor (TI) – High Performance, Low Power, 8-Bit, 1.5 GSPS A/D Converter

ADC081500
www.ti.com
SNAS319G – JUNE 2005 – REVISED APRIL 2013
MULTIPLE ADC SYNCHRONIZATION
The ADC081500 has the capability to precisely reset its sampling clock input to DCLK output relationship as
determined by the user-supplied DCLK_RST pulse. This allows multiple ADCs in a system to have their DCLK
(and data) outputs transition at the same time with respect to the shared CLK input that all the ADCs use for
sampling.
The DCLK_RST signal must observe some timing requirements that are shown in Figure 5, Figure 6 and
Figure 7 of the Timing Diagrams. The DCLK_RST pulse must be of a minimum width and its deassertion edge
must observe setup and hold times with respect to the CLK input rising edge. These timing specifications are
listed as t_RH, t_RS, and t_RPW in the Converter Electrical Characteristics.
The DCLK_RST signal can be asserted asynchronous to the input clock. If DCLK_RST is asserted, the DCLK
output is held in a designated state. The state in which DCLK is held during the reset period is determined by the
mode of operation (SDR/DDR) and the setting of the Output Edge configuration pin or bit. (Refer to Figure 5,
Figure 6 and Figure 7 for the DCLK reset state conditions). Therefore, depending upon when the DCLK_RST
signal is asserted, there may be a narrow pulse on the DCLK line during this reset event. When the DCLK_RST
signal is de-asserted in synchronization with the CLK rising edge, the next CLK falling edge synchronizes the
DCLK output with those of other ADC081500s in the system. The DCLK output is enabled again after a constant
delay (relative to the input clock frequency) which is equal to the CLK input to DCLK output delay (t_SD). The
device always exhibits this delay characteristic in normal operation.
The DCLK_RST pin should NOT be brought high while the calibration process is running (while CalRun is high).
Doing so could cause a digital glitch in the digital circuitry, resulting in corruption and invalidation of the
calibration.
APPLICATIONS INFORMATION
THE REFERENCE VOLTAGE
The voltage reference for the ADC081500 is derived from a 1.254V bandgap reference which is made available
at pin 31, V_BG for user convenience. This output has an output current capability of ±100 μA and should be
buffered if more current than this is required.
The internal bandgap-derived reference voltage has a nominal value of V_IN, as determined by the FSR pin and
described in The Analog Inputs.
There is no provision for the use of an external reference voltage, but the full-scale input voltage can be adjusted
through a Configuration Register in the Extended Control mode, as explained in NORMAL/EXTENDED
CONTROL MODES.
Differential input signals up to the chosen full-scale level will be digitized to 8 bits. Signal excursions beyond the
full-scale range will be clipped at the output. These large signal excursions will also activate the OR output for
the time that the signal is out of range. See Out Of Range (OR) Indication.
One extra feature of the V_BG pin is that it can be used to raise the common mode voltage level of the LVDS
outputs. The output offset voltage (V_OS) is typically 800 mV when the V_BG pin is used as an output or left
unconnected. To raise the LVDS offset voltage to a typical value of 1200 mV the V_BG pin can be connected
directly to the supply rails.
THE ANALOG INPUT
The analog input is a differential one to which the signal source may be a.c. coupled or d.c. coupled. In the
normal mode, the full-scale input range is selected using the FSR pin as specified in the Converter Electrical
Characteristics. In the Extended Control mode, the full-scale input range is selected by programming the Full-
Scale Voltage Adjust register through the Serial Interface. For best performance when adjusting the input full-
scale range in the Extended Control, refer to Table 6 for guidelines on limiting the amount of adjustment.
Table 7 gives the input to output relationship with the FSR pin high when the normal (non-extended) mode is
used. With the FSR pin grounded, the millivolt values in Table 7 are reduced to 75% of the values indicated. In
the Enhanced Control Mode, these values will be determined by the full scale range and offset settings in the
Control Registers.
Copyright © 2005–2013, Texas Instruments Incorporated
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