TMS320VC5503_15 Datasheet, PDF (41/126 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
15
8
7
6
5
4
3
Reserved
IO7D
IO6D
IO5D
(BGA)
IO4D
IO3D
R−00000000
R/W−pin R/W−pin R/W−pin R/W−pin R/W−pin
LEGEND: R = Read, W = Write, pin = value present on the pin (IO7−IO0 default to inputs after reset)
2
IO2D
R/W−pin
1
IO1D
R/W−pin
0
IO0D
R/W−pin
Figure 3−9. I/O Data Register (IODATA) Bit Layout
Table 3−7. I/O Data Register (IODATA) Bit Functions
BIT
BIT
RESET
NO.
NAME
VALUE
FUNCTION
15−8 Reserved
0
These bits are reserved and are unaffected by writes.
7−0
IOxD
pin†‡
IOx Data Bit.
If IOx is configured as an input (IOxDIR = 0 in IODIR):
IOxD = 0
The signal on the IOx pin is low.
IOxD = 1
The signal on the IOx pin is high.
If IOx is configured as an output (IOxDIR = 1 in IODIR):
IOxD = 0
Drive the signal on the IOx pin low.
IOxD = 1
Drive the signal on the IOx pin high.
† _{The GPIO5 pin is available on the BGA package only.}
‡ _{pin = value present on the pin (IO7−IO0 default to inputs after reset)}
3.6.2 Address Bus General-Purpose I/O
The 16 address signals, EMIF.A[15−0], can also be individually enabled as GPIO when the Parallel Port Mode
bit field of the External Bus Selection Register is set for Data EMIF (00) or Multiplexed EHPI mode (11). These
pins are controlled by three registers: the enable register, AGPIOEN, determines if the pins serve as GPIO
or address (Figure 3−10); the direction register, AGPIODIR, determines if the GPIO enabled pin is an input
or output (Figure 3−11); and the data register, AGPIODATA, determines the logic states of the pins in
general-purpose I/O mode (Figure 3−12).
15
AIOEN15
(BGA)
R/W, 0
14
AIOEN14
(BGA)
R/W, 0
13
AIOEN13
R/W, 0
12
AIOEN12
R/W, 0
11
AIOEN11
R/W, 0
10
AIOEN10
R/W, 0
9
AIOEN9
R/W, 0
8
AIOEN8
R/W, 0
7
6
5
AIOEN7
AIOEN6
AIOEN5
R/W, 0
R/W, 0
R/W, 0
LEGEND: R = Read, W = Write, n = value after reset
4
AIOEN4
R/W, 0
3
AIOEN3
R/W, 0
2
AIOEN2
R/W, 0
1
AIOEN1
R/W, 0
Figure 3−10. Address/GPIO Enable Register (AGPIOEN) Bit Layout
0
AIOEN0
R/W, 0
BIT
NO.
15−0
BIT
NAME
AIOENx
Table 3−8. Address/GPIO Enable Register (AGPIOEN) Bit Functions
RESET
VALUE
0
FUNCTION
Enable or disable GPIO function of Address Bus of EMIF. AIOEN15 and AIOEN14 are only available in
BGA package.
AIOENx = 0 GPIO function of Ax line is disabled; i.e., Ax has address function.
AIOENx = 1 GPIO function of Ax line is enabled; i.e., Ax has GPIO function.
April 2004 − Revised January 2008
SPRS245J
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