AFE5805_14 Datasheet, PDF (41/53 Pages) Texas Instruments – FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel

AFE5805
www.ti.com
SBOS421D – MARCH 2008 – REVISED MARCH 2010
APPLICATION INFORMATION
ANALOG INPUT AND LNA
While the LNA is designed as a fully differential
amplifier, it is optimized to perform a single-ended
input to differential output conversion. A simplified
schematic of an LNA channel is shown in Figure 50.
A bias voltage (V_B) of +2.4V is internally applied to
the LNA inputs through 8kΩ resistors. In addition, the
dedicated signal input (IN pin) includes a pair of
back-to-back diodes that provide a coarse input
clamping function in case the input signal rises to
very large levels, exceeding 0.7V_PP. This
configuration prevents the LNA from being driven into
a severe overload state, which may otherwise cause
an extended overload recovery time. The integrated
diodes are designed to handle a dc current of up to
approximately 5mA. Depending on the application
requirements, the system overload characteristics
may be improved by adding external Schottky diodes
at the LNA input, as shown in Figure 50.
As Figure 50 also shows, the complementary LNA
input (V_BL pin) is internally decoupled by a small
capacitor. Furthermore, for each input channel, a
separate V_BL pin is brought out for external
bypassing. This bypassing should be done with a
small, 0.1mF (typical) ceramic capacitor placed in
close proximity to each V_BL pin. Attention should be
given to provide a low-noise analog ground for this
bypass capacitor. A noisy ground potential may
cause noise to be picked up and injected into the
signal path, leading to higher noise levels.
The LNA closed-loop architecture is internally
compensated for maximum stability without the need
of external compensation components (inductors or
capacitors). At the same time, the total input
capacitance is kept to a minimum with only 16pF.
This architecture minimizes any loading of the signal
source that may otherwise lead to a
frequency-dependent voltage divider. Moreover, the
closed-loop design yields very low offsets and offset
drift; this consideration is important because the LNA
directly drives the subsequent voltage-controlled
attenuator.
The LNA of the AFE5805 uses the benefits of a
bipolar process technology to achieve an
exceptionally low-noise voltage of 0.7nV/√Hz, and a
low current noise of only 3pA/√Hz. With these
input-referred noise specifications, the AFE5805
achieves very low noise figure numbers over a wide
range of source resistances and frequencies (see
Figure 16, Noise Figure vs Frequency vs R_S in the
Typical Characteristics). The optimal noise power
matching is achieved for source impedances of
around 200Ω. Further details of the AFE5805 input
noise performance are shown in the Typical
Characteristic graphs.
Table 16. Noise Figure versus Source Resistance
(R_S) at 2MHz
R_S (Ω)
50
NOISE FIGURE (dB)
2.6
200
1.0
400
1.1
1000
2.3
IN
T/R
C_IN
³ 0.1mF
A1
8kW
V_B
(+2.4V)
V_BL
0.1mF
8kW
A2
7pF
To
Attenuator
AFE5805
Figure 50. LNA Channel (Simplified Schematic)
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