AFE5805_14 Datasheet, PDF (29/53 Pages) Texas Instruments – FULLY-INTEGRATED, 8-CHANNEL ANALOG FRONT-END FOR ULTRASOUND 0.85nV/√Hz, 12-Bit, 50MSPS, 122mW/Channel

AFE5805
www.ti.com
SBOS421D – MARCH 2008 – REVISED MARCH 2010
POWER-DOWN MODES
ADDRESS
IN HEX
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
0F
X
0
X
X
0
NAME
PDN_CH<1:4>
PDN_CH<8:5>
PDN_PARTIAL
PDN_COMPLETE
PDN_PIN_CFG
Each of the eight ADC channels within the AFE5805 can be individually powered down. PDN_CH<N> controls
the power-down mode for the ADC channel <N>.
In addition to channel-specific power-down, the AFE5805 also has two global power-down modes: partial
power-down mode and complete power-down mode.
In addition to programming the device for either of these two power-down modes (through either the
PDN_PARTIAL or PDN_COMPLETE bits, respectively), the ADS_PD pin itself can be configured as either a
partial power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when
the ADS_PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when
the ADS_PD pin is high, the device enters partial power-down mode.
The partial power-down mode function allows the AFE5805 to be rapidly placed in a low-power state. In this
mode, most amplifiers in the signal path are powered down, while the internal references remain active. This
configuration ensures that the external bypass capacitors retain the respective charges, minimizing the wake-up
response time. The wake-up response is typically less than 50ms, provided that the clock has been running for at
least 50ms before normal operating mode resumes. The power-down time is instantaneous (less than 1.0ms).
In partial power-down mode, the part typically dissipates only 233mW, representing a 76% power reduction
compared to the normal operating mode. This function is controlled through the ADS_PD and VCA_PD pins,
which are designed to interface with 3.3V low-voltage logic. If separate control of the two PD pins is not desired,
then both can be tied together. In this case, the ADS_PD pin should be configured to operate as a partial
power-down mode pin [see further information (PDN_PIN_CFG) above].
For normal operation the PD pins should be tied to a logic low (0); a high (1) places the AFE5805 into partial
power-down mode.
To achieve the lowest power dissipation of only 64mW, the AFE5805 can be placed in complete power-down
mode. This mode is controlled through the serial interface by setting Register 16 (bit D2) and Register 0F (bit
D9:D10). In complete power-down mode, all circuits (including references) within the AFE5805 are
powered-down, and the bypass capacitors then discharge. Consequently, the wake-up time from complete
power-down mode depends largely on the time needed to recharge the bypass capacitors. Another factor that
affects the wake-up time is the elapsed time that the AFE5805 spends in shutdown mode.
LVDS DRIVE PROGRAMMABILITY
ADDRESS
IN HEX
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
11
X
X
X
X
X
X
NAME
ILVDS_LCLK<2:0>
ILVDS_FRAME<2:0>
ILVDS_DAT<2:0>
The LVDS drive strength of the bit clock (LCLKP or LCLKM) and the frame clock (FCLKP or FCLKM) can be
individually programmed. The LVDS drive strengths of all the data outputs OUTP and OUTM can also be
programmed to the same value.
All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 13
details an example of how the drive strength of the bit clock is programmed (the method is similar for the frame
clock and data drive strengths).
Copyright © 2008–2010, Texas Instruments Incorporated
Product Folder Link(s): AFE5805
Submit Documentation Feedback
29