ADC12D1000RF_15 Datasheet, PDF (40/84 Pages) Texas Instruments – 12-Bit, 3.2-GSPS and 2-GSPS RF-Sampling ADC

ADC12D1000RF, ADC12D1600RF
SNAS519H – JULY 2011 – REVISED AUGUST 2015
www.ti.com
TIME
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
Table 5-2. Test Pattern by Output Port in Demux Mode
Qd
Id
Q
I
ORQ
ORI
000h
004h
008h
010h
0b
0b
FFFh
FFBh
FF7h
FEFh
1b
1b
000h
004h
008h
010h
0b
0b
FFFh
FFBh
FF7h
FEFh
1b
1b
000h
004h
008h
010h
0b
0b
000h
004h
008h
010h
0b
0b
FFFh
FFBh
FF7h
FEFh
1b
1b
000h
004h
008h
010h
0b
0b
FFFh
FFBh
FF7h
FEFh
1b
1b
000h
004h
008h
010h
0b
0b
000h
004h
008h
010h
0b
0b
FFFh
FFBh
FF7h
FEFh
1b
1b
000h
004h
008h
010h
0b
0b
...
...
...
...
...
...
COMMENTS
Pattern
Sequence
n
Pattern
Sequence
n+1
Pattern
Sequence
n+2
When the part is programmed into the Non-Demux Mode, the test pattern’s order is described in Table 5-
3.
TIME
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
Table 5-3. Test Pattern by Output Port in Non-Demux Mode
Q
I
ORQ
ORI
000h
004h
0b
0b
000h
004h
0b
0b
FFFh
FFBh
1b
1b
FFFh
FFBh
1b
1b
000h
004h
0b
0b
FFFh
FFBh
1b
1b
000h
004h
0b
0b
FFFh
FFBh
1b
1b
FFFh
FFBh
1b
1b
FFFh
FFBh
1b
1b
000h
004h
0b
0b
000h
004h
0b
0b
FFFh
FFBh
1b
1b
FFFh
FFBh
1b
1b
...
...
...
...
COMMENTS
Pattern Sequence
n
Pattern Sequence
n+1
5.3.2.6 Time Stamp
The Time Stamp feature enables the user to capture the timing of an external trigger event, relative to the
sampled signal. When enabled through the TSE Bit (Addr: 0h; Bit: 3), the LSB of the digital outputs (DQd,
DQ, DId, DI) captures the trigger information. In effect, the 12-bit converter becomes an 11-bit converter
and the LSB acts as a 1-bit converter with the same latency as the 11-bit converter. The trigger should be
applied to the DCLK_RST input. It may be asynchronous to the ADC sampling clock.
40
Detailed Description
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