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TS3A5018_14 Datasheet, PDF (4/38 Pages) Texas Instruments – 10-Ω QUAD SPDT ANALOG SWITCH
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TS3A5018
SCDS189F – JANUARY 2005 – REVISED MAY 2013
www.ti.com
Electrical Characteristics for 3.3-V Supply(1)
V+ = 3 V to 3.6 V, TA = –40°C to 85°C (unless otherwise noted)
PARAMETER SYMBOL
TEST CONDITIONS
Analog Switch
Analog signal
range
VCOM, VNO,
VNC
ON-state
resistance
ron
0 ≤ (VNC or VNO) ≤ V+,
ICOM = –32 mA,
Switch ON,
See Figure 19
ON-state
resistance
match between
Δron
VNC or VNO = 2.1 V,
ICOM = –32 mA,
channels
Switch ON,
See Figure 19
ON-state
resistance
flatness
ron(flat)
0 ≤ (VNC or VNO) ≤ V+,
ICOM = –32 mA,
Switch ON,
See Figure 19
NC, NO
OFF leakage
current
INC(OFF),
INO(OFF)
VNC or VNO = 1 V,
VCOM = 3 V,
or
VNC or VNO = 3 V,
VCOM = 1 V,
VNC or VNO = 0 to 3.6 V,
VCOM = 3.6 V to 0,
or
VNC or VNO = 3.6 V to 0,
VCOM = 0 to 3.6 V,
COM
OFF leakage
current
ICOM(OFF)
VCOM = 1 V,
VNC or VNO = 3 V,
or
VCOM = 3 V,
VNC or VNO = 3 V,
VCOM = 0 to 3.6 V,
VNC or VNO = 3.6 V to 0,
or
VCOM = 3.6 V to 0,
VNC or VNO = 0 to 3.6 V,
NC, NO
ON leakage
current
INC(ON),
INO(ON)
VNC or VNO = 1 V,
VCOM = Open,
or
VNC or VNO = 3 V,
VCOM = Open,
COM
ON leakage
current
ICOM(ON)
VCOM = 1 V,
VNC or VNO = Open,
or
VCOM = 3 V,
VNC or VNO = Open,
Digital Control Inputs (IN, EN)(2)
Switch OFF,
See Figure 20
Switch OFF,
See Figure 20
Switch OFF,
See Figure 20
Switch OFF,
See Figure 20
Switch ON,
See Figure 21
Switch ON,
See Figure 21
Input logic high
VIH
Input logic low
VIL
Input leakage
current
IIH, IIL
VI = V+ or 0
TA
V+
MIN TYP MAX UNIT
25°C
Full
25°C
Full
25°C
Full
25°C
Full
3V
3V
3V
3.6 V
25°C
0V
Full
25°C
Full
3.6 V
25°C
0V
Full
25°C
Full
3.6 V
25°C
Full
3.6 V
0
7
0.3
5
–0.1 0.05
–0.2
–2 0.05
–10
–0.1 0.05
–0.2
–2 0.05
–10
–0.1 0.05
–0.2
–0.1 0.05
–0.2
V+ V
10
Ω
12
0.8
Ω
1
7
Ω
8
0.1
0.2
μA
2
10
0.1
0.2
μA
2
10
0.1
μA
0.2
0.1
μA
0.2
Full
Full
25°C
Full
3.6 V
2
0
–1 0.05
–1
V+ V
0.8 V
1
μA
1
(1) The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
(2) All unused digital inputs of the device must be held at V+ or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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