TLC6C5912-Q1 Datasheet, PDF (4/26 Pages) Texas Instruments – TLC6C5912-Q1 Power Logic 12-Channel Shift Register LED Driver

TLC6C5912-Q1
SLIS141C – DECEMBER 2012 – REVISED JULY 2016
www.ti.com
NAME
PIN
NO.
SER OUT
11
SRCK
19
V_CC
1
Pin Functions (continued)
I/O
DESCRIPTION
Serial-data output: SER OUT is the serial data output of the 12−bit serial shift register. The
purpose of this pin is to cascade several devices on the serial bus. By connecting the SER
O
OUT pin to the SER IN input of the next device on the serial bus to cascade, the data
transfers to the next device on the falling edge of SRCK. This can improve the cascade
application reliability, as it can avoid the issue that the second device receives SRCK and
data input at the same rising edge of SRCK.
I
Shift-register clock: SRCK is the serial clock input. On each rising SRCK edge, data
transfers from SER IN to the internal serial shift registers.
I
Power supply: V_CC is the power supply pin voltage for the device. TI recommends adding a
0.1 μF ceramic capacitor close to the pin.
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
MIN
MAX
UNIT
V_CC Logic supply voltage
V_I Logic input-voltage
V_DS Power DMOS drain-to-source voltage
Continuous total dissipation
8
V
–0.3
8
V
42
V
See Thermal Information
Operating ambient temperature (Top)
125
°C
T_J Operating junction temperature
T_stg Storage temperature
–40
150
°C
–55
165
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human body model (HBM), per AEC Q100-002⁽¹⁾
Charged device model (CDM), per AEC Q100-011
VALUE
±2000
±750
(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
UNIT
V
6.3 Recommended Operating Conditions
V_CC Supply voltage
V_IH High-level input voltage
V_IL
Low-level input voltage
t_su
Setup time, SER IN high before SRCK↑
t_h
Hold time, SER IN high after SRCK↑
t_w
Pulse duration
T_C
Operating case temperature
MIN MAX UNIT
3 5.5 V
2.4
V
0.7 V
15
ns
15
ns
40
ns
–40 125 °C
4
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