TLC6C5912-Q1 Datasheet, PDF (3/26 Pages) Texas Instruments – TLC6C5912-Q1 Power Logic 12-Channel Shift Register LED Driver

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5 Pin Configuration and Functions
TLC6C5912-Q1
SLIS141C – DECEMBER 2012 – REVISED JULY 2016
PW Package
20-Pin TSSOP
Top View
DW Package
20-Pin SOIC
Top View
VCC
1
SER IN
2
DRAIN0
3
DRAIN1
4
DRAIN2
5
DRAIN3
6
DRAIN4
7
DRAIN5
8
CLR
9
G
10
Not to scale
NAME
PIN
NO.
CLR
9
DRAIN0
3
DRAIN1
4
DRAIN2
5
DRAIN3
6
DRAIN4
7
DRAIN5
8
DRAIN6
13
DRAIN7
14
DRAIN8
15
DRAIN9
16
DRAIN10
17
DRAIN11
18
G
10
GND
20
RCK
12
SER IN
2
20
GND
19
SRCK
18
DRAIN11
17
DRAIN10
16
DRAIN9
15
DRAIN8
14
DRAIN7
13
DRAIN6
12
RCK
11
SER OUT
VCC
1
SER IN
2
DRAIN0
3
DRAIN1
4
DRAIN2
5
DRAIN3
6
DRAIN4
7
DRAIN5
8
CLR
9
G
10
20
GND
19
SRCK
18
DRAIN11
17
DRAIN10
16
DRAIN9
15
DRAIN8
14
DRAIN7
13
DRAIN6
12
RCK
11
SER OUT
Not to scale
Pin Functions
I/O
DESCRIPTION
Shift register clear, active-low: CLR is the signal used to clear all the registers. The
I
storage register transfers data to the output buffer when shift register clear CLR is high.
Driving CLR is low clears all the registers in the device.
O
O
O
O
O
O
Open-drain output: DRAIN0 to DRAIN11 are the LED current-sink channels. These pins
connect to the LED cathodes, and they can survive up to 40-V LED supply voltage. This is
O
quite helpful during automotive load-dump conditions.
O
O
O
O
O
Output enable, active-low: G is the LED channel enable and disable input pin. Having G
I
low enables all drain channels according to the output-latch register content. When high, all
channels are off.
—
Power ground: GND is the ground reference pin for the device. This pin must connect to the
ground plane on the PCB.
Register clock: RCK is the storage register clock. The data in each shift register stage
I
transfers to the storage register at the rising edge of RCK. Data in the storage register
appears at the output whenever the output enable G̅ input signal is high.
I
Serial-data input: SER IN is the serial data input. Data on SER IN loads into the internal
register on each rising edge of SRCK.
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