TLC542C_14 Datasheet, PDF (4/13 Pages) Texas Instruments – 8-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 INPUTS

TLC542C, TLC542I
8-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 11 INPUTS
SLAS075C – FEBRUARY 1989 – REVISED JUNE 2001
recommended operating conditions, V_CC = 4.75 to 5.5 V
MIN NOM
MAX
UNIT
Supply voltage, VCC
Positive reference voltage, Vref ₊ (see Note 2)
Negative reference voltage, Vref _– (see Note 2)
Differential reference voltage, Vref+ – Vref_– (see Note 2)
Analog input voltage (see Note 3)
High-level control input voltage, VIH
Low-level control input voltage, VIL
Setup time, address bits at data input before I/O CLOCK↑, tsu(A)
Hold time, address bits after I/O CLOCK↑, th(A)
Hold time, CS low after 8th I/O CLOCK↑, th(CS)
Setup time, CS low before clocking in first address bit, tsu(CS) (see Note 4)
Input/output clock frequency, f(clock _I/O)
Input/output clock high, tw(H _I/O)
Input/output clock low, tw(L _I/O)
I/O CLOCK transition time, tt (see Note 3)
fclock(I/O) ≤ 525 kHz
fclock(I/O) > 525 kHz
Operating free-air temperature, TA
TLC542C
TLC542I
4.75
Vref_–
– 0.1
1
0
2
400
0
0
3.8
0
404
404
0
– 40
5
VCC
0
VCC
5.5
VCC + 0.1
Vref+
VCC + 0.2
VCC
0.8
1.1
100
40
70
85
V
V
V
V
V
V
V
ns
ns
ns
µs
MHz
ns
ns
ns
°C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (11111111), while input voltages less than that applied
to REF – convert as all zeros (00000000). For proper operation, REF+ must be at least 1 V higher than REF –. Also, the total
unadjusted error may increase as this differential reference voltage falls below 4.75 V.
3. This is the time required for the clock input signal to fall from VIH min to VIL max or to rise from VIL max to VIH min. In the vicinity
of normal room temperature, the devices function with input clock transition time as slow as 2 µs for remote data acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.
4. To minimize errors caused by noise at the chip select input, the internal circuitry waits for two rising edges and one falling edge of
the internal system clock after CS ↓ before responding to control input signals. The CS setup time is given by the tsu(CS)
specifications. Therefore, no attempt should be made to clock-in address data until the minimum chip select setup time has elapsed.
electrical characteristics over recommended operating temperature range, V_CC = V_ref+ = 4.75 V to
5.5 V, f_{(clock I/O)} = 1.1 MHz (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN TYP^† MAX UNIT
VOH High-level output voltage (DATA OUT)
VCC = 4.75 V,
IOH = – 360 µA
2.4
V
VOL Low-level output voltage
VCC = 4.75 V,
IOL = 1.6 mA
0.4 V
Off-state (high-impedance state) output current
IIH High-level input current
IIL Low-level input current
VO = VCC,
VO = 0,
VI = VCC
VI = 0
CS at VCC
CS at VCC
10
µA
–10
0.005
2 µA
– 0.005 – 2.5 µA
ICC Operating supply current
CS at 0 V
1.2
2 mA
Selected channel leakage current
Selected channel at VCC and
unselected channel at 0 V
Selected channel at 0 V and
unselected channel at VCC
0.4
µA
– 0.4
Iref Maximum static analog reference current into REF+
Ci Input capacitance
Analog inputs
Control inputs
Vref+ = VCC,
Vref _– = GND
10 µA
7
55
pF
5
15
† _{All typical values are at TA = 25°C.}
4
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