TLC320AD58 Datasheet, PDF (4/27 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

List of Illustrations
Figure
Title
Page
2–1. Power-Down Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2–2. Differential Analog Input Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2
2–3. Serial Master Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
2–4. Serial Slave Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
4–1. SCLK to Fsync and DOUT – Master Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4–2. SCLK to Fsync, DOUT, and LRClk – Master Modes 4 and 6 . . . . . . . . . . . . . . . . . . . . . 4–1
4–3. SCLK to Fsync, DOUT, and LRClk – Master Mode 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1
4–4. SCLK to Fsync, DOUT, and LRClk – Master Mode 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–5. SCLK to LRClk and DOUT – Slave Mode 0, Fsync High . . . . . . . . . . . . . . . . . . . . . . . . 4–2
4–6. SCLK to Fsync, LRClk, and DOUT – Slave Mode 2, Fsync Controlled . . . . . . . . . . . . 4–2
5–1. TLC320AD58C Configuration Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–2
5–2. TLC320AD58C External Digital Timing and Control-Signal Generation Schematic . 5–3
5–3. TLC320AD58C External Analog Input Buffer Schematic . . . . . . . . . . . . . . . . . . . . . . . . 5–4
List of Tables
Table
Title
Page
2–1. Master-Clock to Sample-Rate Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
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