TLC320AD58 Datasheet, PDF (13/27 Pages) Texas Instruments – Sigma-Delta Stereo Analog-to-Digital Converter

Mode 011
SCLK
Fsync
DOUT
LRClk
(a) 16-BIT MASTER MODE (Fsync bound)
15 14 ^{. . .} 1 0
15 14 ^{. . .} 1 0
64 SCLKs
Left
Right
Mode 100
SCLK
Fsync
(b) 18-BIT MASTER MODE
DOUT
17 16
... 1 0
17 16 . . .
10
17
LRClk
Left
64 SCLKs
Right
Mode 101
SCLK
Fsync
DOUT
LRClk
Mode 110
SCLK
Fsync
DOUT
LRClk
Mode 111
SCLK
Fsync
DOUT
LRClk
(c) 18-BIT MASTER MODE
01
. . . 16 17
01
. . . 16 17
64 SCLKs
Left
Right
(d) 16-BIT DSP CONTINUOUS MODE
15
14
Left
... ₁
0
15
14
32 SCLKs
Right
(e) 16-BIT DSP CONTINUOUS MODE
... ₁
0
15
0
1
Left
. . . ₁₄
15
0
1
32 SCLKs
Right
. . . ₁₄
15
0
Figure 2–3. Serial Master Transfer Modes
2.8.2 Slave Mode
As a slave, the TLC320AD58C receives LRClk, Fsync, and SCLK as inputs. The conversion cycle is
synchronized to the rising edge of LRClk, and the data is synchronized to the falling edge of SCLK. SCLK
must meet the setup requirements specified in the recommended operating conditions section.
Synchronization of the slave modes is accomplished with the digital power-down control.
In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2–4(a) through 2–4(c).
SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a
power-down cycle initiate the conversion cycle. Refer to the master-mode section for signal functions.
2–5