THS1209 Datasheet, PDF (4/33 Pages) Texas Instruments – 12-BIT, 2 ANALOG INPUT, 8MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
www.ti.com
ELECTRICAL CHARACTERISTICS
over recommended operating conditions, VREF = internal, fs = 8 MSPS, fI = 2 MHz at –1 dBFS (unless otherwise noted)
AC SPECIFICATIONS, AVDD = DVDD = 5 V, BVDD = 3.3 V, CL < 30 pF
PARAMETER
TEST CONDITIONS
MIN TYP
SINAD Signal-to-noise ratio + distortion
Differential mode
Single-ended mode
63
65
62
64
SNR Signal-to-noise ratio
Differential mode
Single-ended mode
64
69
64
68
THD Total harmonic distortion
Differential mode
–70
Single-ended mode
–68
ENOB _{Effective number of bits}
(SNR)
Differential mode
Single-ended mode
10.17 10.5
10 10.3
SFDR Spurious free dynamic range
Differential mode
Single-ended mode
67
71
65
69
Analog Input
Full-power bandwidth with a source impedance of 150 Ω in
differential configuration.
Full scale sinewave, –3 dB
98
Full-power bandwidth with a source impedance of 150 Ω in
single-ended configuration.
Full scale sinewave, –3 dB
54
Small-signal bandwidth with a source impedance of 150 Ω in
differential configuration.
100 mVpp sinewave, –3 dB
98
Small-signal bandwidth with a source impedance of 150 Ω in
single-ended configuration.
100 mVpp sinewave, –3 dB
54
MAX
–67
–64
UNIT
dB
dB
dB
dB
dB
dB
Bits
Bits
dB
dB
MHz
MHz
MHz
MHz
TIMING REQUIREMENTS
AVDD = DVDD = 5 V, BVDD = 3.3 V, VREF = internal, CL < 30 pF
PARAMETER
tpipe
tsu(CONV_CLKL-READL)
tsu(READH-CONV_CLKL)
td(CONV_CLKL-SYNCL)
td(CONV_CLKL-SYNCH)
Latency
Setup time, CONV_CLK low before CS valid
Setup time, CS invalid to CONV_CLK low
Delay time, CONV_CLK low to SYNC low
Delay time, CONV_CLK low to SYNC high
TEST CONDITIONS
MIN TYP MAX UNIT
5
CONV
CLK
10
ns
20
ns
10 ns
10 ns
4