THS1209 Datasheet, PDF (16/33 Pages) Texas Instruments – 12-BIT, 2 ANALOG INPUT, 8MSPS, SIMULTANEOUS SAMPLING ANALOG-TO-DIGITAL CONVERTER

THS1209
SLAS288B – JULY 2000 – REVISED DECEMBER 2002
www.ti.com
Figure 26 shows the conversion timing when two analog input channels are selected. The maximum throughput rate
per channel is 4 MSPS in this mode. The data flow in the bottom of the figure shows the order the converted data
is available to the data bus. The SYNC signal is always active low if data of channel 1 is available to the data bus.
There is a certain timing relationship required for the read signal with respect to the conversion clock. This can be
seen in Figure 26 and with the timing specifications. A more detailed description of the timing is given in the section
timing and signal description of the THS1209.
Sample N
Channel 1, 2
Sample N+1
Channel 1, 2
AIN
td(A)
td(pipe)
tw(CONV_CLKH)
tw(CONV_CLKL)
CONV_CLK
tc
tsu(CONV_CLKL-READL)
Sample N+2
Channel 1, 2
tsu(READH-CONV_CLKL)
Sample N+3
Channel 1, 2
READ^†
SYNC
td(CONV_CLKL-SYNCL)
td(CONV_CLKL-SYNCH)
Data N–2
Channel 1
Data N–2
Channel 2
Data N–1
Channel 1
Data N–1
Channel 2
Data N
Channel 1
Data N
Channel 2
†_{READ is the logical combination from CS0, CS1 and RD}
Figure 26. Conversion Timing in 2 Channel Operation
Data N+1
Channel 1
16