SN74LVC2G125_16 Datasheet, PDF (4/22 Pages) Texas Instruments – Dual Bus Buffer Gate With 3-State Outputs

SN74LVC2G125
SCES204P – APRIL 1999 – REVISED JANUARY 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
See ⁽¹⁾
V_CC Supply voltage range
V_I
Input voltage range⁽²⁾
V_O Voltage range applied to any output in the high-impedance or power-off state⁽²⁾
V_O Voltage range applied to any output in the high or low state⁽²⁾⁽³⁾
I_IK Input clamp current
V_I < 0
I_OK Output clamp current
V_O < 0
I_O Continuous output current
Continuous current through V_CC or GND
T_stg Storage temperature range
T_J Junction temperature
MIN
MAX UNIT
–0.5
6.5 V
–0.5
6.5 V
–0.5
6.5 V
–0.5 V_CC + 0.5 V
–50 mA
–50 mA
±50 mA
±100 mA
–65
150 °C
150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(3) The value of V_CC is provided in the Recommended Operating Conditions table.
6.2 ESD Ratings
PARAMETER
V_(ESD)
Electrostatic
discharge
DEFINITION
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾
Charged device model (CDM), per JEDEC specification JESD22-C101,
all pins⁽²⁾
VALUE
2000
1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
4
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