SN74CBT3251_15 Datasheet, PDF (4/25 Pages) Texas Instruments – FET Multiplexer and Demultiplexer

SN74CBT3251
SCDS019M – MAY 1995 – REVISED DECEMBER 2015
6 Specifications
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6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
Supply voltage, V_CC
Input voltage, V_I(2)
Continuous channel current
Input clamp current, I_K (V_I/O < 0)
Maximum junction temperature, T_J
Storage temperature, T_stg
MIN
MAX
UNIT
–0.5
7
V
–0.5
7
V
128
mA
–50
mA
150
°C
–65
150
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
6.2 ESD Ratings
V_(ESD)
Electrostatic
discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
VALUE
±1500
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V_CC
Supply voltage
V_IH
High-level control input voltage
V_IL
Low-level control input voltage
T_A
Operating free-air temperature
MIN
MAX
UNIT
4
5.5
V
2
V
0.8
V
–40
85
°C
6.4 Thermal Information
SN74CBT3251
THERMAL METRIC⁽¹⁾
D
(SOIC)
DB
(SSOP)
DBQ
PW
RGY
(SSOP) (TSSOP) (VQFN)
UNIT
R_θJA
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
16 PINS
73 ⁽²⁾
70.6
77.8
24.3
77.4
—
16 PINS
82 ⁽²⁾
49.0
49.4
10.5
48.8
—
16 PINS
90 ⁽²⁾
59.0
50.1
13.9
49.7
—
16 PINS
108 ⁽²⁾
41.6
51.9
4.0
51.3
—
16 PINS
39 ⁽³⁾
52.8
20.4
1.1
20.4
6.4
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
(3) The package thermal impedance is calculated in accordance with JESD 51-5.
4
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