SN74ACT72211L Datasheet, PDF (4/21 Pages) Texas Instruments – SYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES

SN74ACT72211L, SN74ACT72221L, SN74ACT72231L, SN74ACT72241L
512 × 9, 1024 × 9, 2048 × 9, AND 4096 × 9
SYNCHRONOUS FIRSTĆIN, FIRSTĆOUT MEMORIES
SCAS222 − FEBRUARY 1993 − REVISED JUNE 1993
detailed description
device reset
A reset is performed by taking the reset (RS) input low. This initializes both the write and read pointers to the
first memory location. After a reset, the full flag (FF) and programmable almost-full flag (PAF) are high and the
empty flag (EF) and programmable almost-empty flag (PAE) are low. Each bit in the data output register
(Q0 −Q8) is set low, and the flag offset registers are loaded with the default offset values. A FIFO must be reset
after power up before a write cycle is allowed.
The logic level on the dual-purpose input write enable 2/ load (WEN2/LD) during reset determines its function.
If WEN2/LD is high when RS returns high at the end of the reset cycle, the input is a second write enable (see
FIFO writes and reads) and the programmable flags (PAF, PAE) can only use the default values. If WEN2/LD
is low when RS returns high at the end of the reset cycle, the input is the load (LD) enable for writing and reading
flag offset registers (see flag programming).
FIFO writes and reads
Data is written to memory by a low-to-high transition of write clock (WCLK) when write enable 1 (WEN1) is low,
WEN2/LD is high, and FF is high. This stores D0 −D8 data in the dual-port SRAM and increments the write
pointer.
If no reads are performed after reset (RS = V_IL ), FF is set low upon the completion of 512 writes to the
SN74ACT72211, 1024 writes to the SN74ACT72221, 2048 writes to the SN74ACT72231, and 4096 writes to
the SN74ACT72241. Attempted write cycles are ignored when FF is low. FF is set high by the first low-to-high
transition of WCLK after data is read from a full FIFO. FF and PAF are each synchronized to the low-to-high
transition of WCLK by one flip-flop.
If a device is configured to have two write enables (see device reset), data is read by the low-to-high transition
of read clock (RCLK) when both read enables (REN1, REN2) are low and EF is high. WEN2/LD must also be
high if the device is configured to have programmable flags. A read from the FIFO puts RAM data on Q0−Q8
and increments the read pointer in the same sequence as the write pointer. New data is not shifted to the output
register while either one or both of the read enables are high.
EF and PAE are each synchronized to the low-to-high transition of RCLK by one flip-flop. When the device is
empty, the write and read pointers are equal and EF is set low. Attempted read cycles are ignored while EF is
set low. EF is set high by the first low-to-high transition of RCLK after data is written to an empty FIFO.
WCLK and RCLK can be asynchronous or coincident to one another. Writing data to FIFO memory is
independent of reading data from FIFO memory and vice versa.
flag programming
When WEN2/LD is held low during a device reset (RS = V_IL ), the input is the load (LD) enable for flag offset
programming. In this configuration, WEN2/LD can be used to access the four 8-bit offset registers contained
in the SN74ACT72211L / -72221L / -72231L / -72241L for writing or reading data.
When the device is configured for programmable flags and both WEN2/LD and WEN1 are low, the first
low-to-high transition of WCLK writes data from the data inputs to the empty offset least significant bit (LSB)
register. The second, third, and fourth low-to-high transitions of WCLK store data in the empty offset most
significant bit (MSB) register, full offset LSB register, and full offset MSB register, respectively, when WEN2/LD
and WEN1 are low. The fifth low-to-high transition of WCLK while WEN2/LD and WEN1 are low writes data to
the empty LSB register again. Figure 1 shows the register sizes and default values for the various device types.
It is not necessary to write to all the offset registers at one time. A subset of the offset registers can be written;
then, by bringing the WEN2/LD input high, the FIFO is returned to normal read and write operation. The next
time WEN2/LD is brought low, a write operation stores data in the next offset register in sequence.
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