SM320DM642-HIREL Datasheet, PDF (4/170 Pages) Texas Instruments – SM320DM642-HiRel Video/Imaging Fixed Point Digital Signal Processor

SM320DM642-HiRel
SGUS063A – JUNE 2009 – REVISED OCTOBER 2010
1.2 Functional Block Diagram
Figure 1-1 shows the functional block diagram of the DM642 device.
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SDRAM
SBSRAM
ZBT SRAM
FIFO
SRAM
ROM/FLASH
I/O Devices
(B)
64
EMIF A
Timer 2
Timer 1
Timer 0
VCXO
Interpolated
Control Port
(VIC)
Video Port 2
(VP2)
Video Port 0
(VP0)
OR
8/10-bit VP0
AND
McBSP0^(A)
OR
McASP0
Control
Video Port 1
(VP1)
OR
8/10-bit VP1
AND
McBSP1^(A)
OR
McASP0
Data
Enhanced
DMA
Controller
(EDMA)
L2
Cache
Memory
256kBytes
TMS320DM642
L1P Cache
Direct-Mapped
16K Bytes Total
C64x DSP Core
Instruction Fetch
Instruction Dispatch
Advanced Instruction Packet
Instruction Decode
Data Path A
Data Path B
A Register File
A31−A16
A15−A0
B Register File
B31−B16
B15−B0
Control
Registers
Control
Logic
Test
Advanced
In-Circuit
Emulation
.L1 .S1 .M1 .D1
.D2 .M2 .S2 .L2
Interrupt
Control
L1D Cache 2-Way Set-Associative
16K Bytes Total
PLL
(x1, x6, x12)
Power-Down
Logic
PCI-66
OR
HPI32
OR
HPI16
AND/OR
EMAC
MDIO
Boot Configuration
16
GP0
2
I2C0
A. McBSPs: Framing Chips – H.100, MVIP, SCSA, T1, E1; AC97 Devices; SPI Devices; Codecs
B. The Video Port 0 (VP0) peripheral is muxed with the McBSP0 peripheral and the McASP0 control pins. The Video
Port 1 (VP1) peripheral is muxed with the McBSP1 peripheral and the McASP0 data pins. The PCI peripheral is
muxed with the HPI(32/16), EMAC, and MDIO peripherals. For more details on the multiplexed pins of these
peripherals, see the Device Configurations section of this data sheet.
Figure 1-1. Functional Block Diagram
4
SM320DM642-HiRel Video/Imaging Fixed-Point Digital Signal Processor
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