SM320DM642-HIREL Datasheet, PDF (164/170 Pages) Texas Instruments – SM320DM642-HiRel Video/Imaging Fixed Point Digital Signal Processor

SM320DM642-HiRel
SGUS063A – JUNE 2009 – REVISED OCTOBER 2010
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5.20 JTAG
The JTAG interface is used for BSDL testing and emulation of the DM642 device.
Note: IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
5.20.1 JTAG Device-Specific Information
5.20.1.1 IEEE 1149.1 JTAG Compatibility Statement
The DM642 DSP requires that both TRST and RESET be asserted upon power up to be properly
initialized. While RESET initializes the DSP core, TRST initializes the DSP's emulation logic. Both resets
are required for proper operation.
Note: TRST is synchronous and must be clocked by TCLK; otherwise, BSCAN may not respond as
expected after TRST is asserted.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the DSP to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG port
interface and DSP's emulation logic in the reset state. TRST only needs to be released when it is
necessary to use a JTAG controller to debug the DSP or exercise the DSP's boundary scan functionality.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, the DM642 DSP includes an internal pulldown (IPD) on the TRST pin to ensure
that TRST will always be asserted upon power up and the DSP's internal emulation logic will always be
properly initialized. JTAG controllers from Texas Instruments actively drive TRST high. However, some
third-party JTAG controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to intialize the DSP after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations.
Following the release of RESET, the low-to-high transition of TRST must be "seen" to latch the state of
EMU1 and EMU0. The EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation
mode. For more detailed information, see the terminal functions section of this data sheet.
Note: The DESIGN_WARNING section of the DM642 BSDL file contains information and constraints
regarding proper device operation while in Boundary Scan Mode.
5.20.1.2 JTAG ID Register Description
The JTAG ID register is a read-only register that identifies to the customer the JTAG/Device ID. For the
DM642 device, the JTAG ID register resides at address location 0x01B3 F008. The register hex value for
the DM642 device is: 0x0007 902F. For the actual register bit names and their associated bit field
descriptions, see Figure 5-73 and Table 5-89.
31-28
27-12
VARIANT (4-Bit)
PART NUMBER (16-Bit)
R-0000
R-0000 0000 0111 1001
Legend: R = Read only, -n = value after reset
11-1
0
MANUFACTURER (11-Bit)
LSB
R-0000 0010 111
R-1
Figure 5-73. JTAG ID Register Description – DM642 Register Value – 0x0007 902F
164 DM642 Peripheral Information and Electrical Specifications
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