SLVS141A Datasheet, PDF (4/18 Pages) Texas Instruments – FIXED NEGATIVE 5-V 200-mA INVERTING DC/DC CONVERTER

TPS6735
FIXED NEGATIVE 5ĆV 200ĆmA INVERTING DC/DC CONVERTER
SLVS141A − JULY 1996 − REVISED JANUARY 1997
detailed description
The following descriptions refer to the functional block diagram.
current-sense amplifier
The current-sense amplifier, which has a fixed gain of 3, amplifies the slope-compensated current-sense
voltage (a summation of the voltage on the current-sense resistor and the oscillator ramp) and feeds it to the
PWM comparator.
driver latch
The latch, which consists of a set/reset flip-flop and associated logic, controls the state of the power switch by
turning the driver on and off. A high output from the latch turns the switch on; a low output turns it off. In normal
operation the flip-flop is set high during the clock pulse, but gating keeps the latch output low until the clock pulse
is over. The latch is reset when the PWM comparator output goes high.
enable (EN)
A logic low on EN puts the TPS6735 in shutdown mode. In shutdown, the output power switch, voltage
reference, and other functions shut off and the supply current is reduced to 1-µA maximum. The soft-start
capacitor is discharged through a 1.2-MΩ resistance and the output falls to zero volts.
error amplifier
The error amplifier is a high-gain differential amplifier used to regulate the converter output voltage. The
amplifier generates an error signal, which is fed to the PWM comparator, by comparing a sample of the output
voltage to the reference and amplifying the difference. The output sample is obtained from a resistive divider
connected between FB and REF. FB is connected externally to the converter output, and the divider output is
connected to the error-amplifier input. An 82-pF capacitor connected between COMP and GND is required to
stabilize the control loop for loads greater than 100 mA.
oscillator and ramp generator
The oscillator circuit provides a 160-kHz clock to set the converter operating frequency, and a timing ramp for
slope compensation. The clock waveform is a pulse, a few hundred nanoseconds in duration, that is used to
limit the maximum power switch duty cycle to 95%. The timing ramp is summed with the current-sense signal
at the input to the current-sense amplifier.
overcurrent comparator
The overcurrent comparator monitors the current in the power switch. The comparator trips and initiates a
soft-start cycle if the power-switch current exceeds 2 A peak.
power switch
The power switch is a 0.4-Ω p-channel MOSFET with current sensing. The drain is connected to OUT and the
current sense is connected to a resistor. The voltage across the resistor is proportional to current in the power
switch and is tied to the overcurrent comparator and the current-sense amplifier. In normal operation, the power
switch is turned on at the start of each clock cycle and turned off when the PWM comparator resets the drive
latch.
PWM comparator
The comparator resets the drive latch and turns off the power switch whenever the slope-compensated
current-sense signal from the current-sense amplifier exceeds the error signal.
reference
The 1.22-V reference is brought out on REF and can source 125-µA maximum to external loads. A 10-µF
capacitor connected between REF and GND is recommended to minimize noise pickup.
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