LP2954 Datasheet, PDF (4/28 Pages) National Semiconductor (TI) – 5V and Adjustable Micropower Low-Dropout Voltage Regulators

LP2954, LP2954A
SNVS096E – JUNE 1999 – REVISED JULY 2016
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾
Input supply voltage
Power dissipation⁽¹⁾
Storage temperature, T_stg
MIN
MAX
–20
30
Internally Limited
–65
150
UNIT
V
°C
(1) At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heat sink values (if a
heat sink is used). If power dissipation causes the junction temperature to exceed specified limits, the device goes into thermal
shutdown.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
VALUE
±2000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
Operating junction temperature
MIN
NOM
MAX UNIT
–40
125
°C
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
LP2954, LP2954A
KTT (DDPAK/TO-263) NDE (TO-220)
D (SOIC)
UNIT
R_θJA ⁽²⁾
R_θJC(top)
R_θJB
ψ_JT
ψ_JB
R_θJC(bot)
Junction-to-ambient thermal resistance, High-K
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
3 PINS
44.3
44.8
23.8
10.6
22.7
1.0
3 PINS
80.3 ⁽³⁾
38.6
73.1
13.5
73.1
0.9
8 PINS
105.0
47.3
45.8
6.2
45.2
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
(2) Thermal resistance value R_θJA is based on the EIA/JEDEC High-K printed circuit board defined by JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
(3) The TO-220 (NDE) package is vertically mounted in center of JEDEC High-K test board (JESD 51-7) with no additional heat sink. This is
a through-hole package; this is NOT a surface mount package.
4
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