LP2954 Datasheet, PDF (18/28 Pages) National Semiconductor (TI) – 5V and Adjustable Micropower Low-Dropout Voltage Regulators

LP2954, LP2954A
SNVS096E – JUNE 1999 – REVISED JULY 2016
10 Layout
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10.1 Layout Guidelines
For best overall performance, place all the circuit components on the same side of the circuit board and as near
as practical to the respective LDO pin connections. Place ground return connections to the input and output
capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side,
copper surface. The use of vias and long traces to create LDO circuit connections is strongly discouraged and
negatively affects system performance. This grounding and layout scheme minimizes inductive parasitic, and
thereby reduces load-current transients, minimizes noise, and increases circuit stability.
TI also recommends a ground reference plane and is either embedded in the PCB itself or located on the bottom
side of the PCB opposite the components. This reference plane serves to assure accuracy of the output voltage,
shield noise, and behaves similar to a thermal plane to spread heat from the LDO device. In most applications,
this ground plane is necessary to meet thermal requirements.
10.2 Layout Example
Ground
1
2
3
Input
Output
Capacitor Capacitor
VIN
VOUT
Figure 25. LP2954 TO-263 Board Layout
VOUT
Output
Capacitor
OUT
SENSE
SHUTDOWN
GND
Ground
Input
Capacitor
IN
VIN
FEEDBACK
5V TAP
ERROR
Error Pullup
Resistor
VOUT
Figure 26. LP2954 SOIC Board Layout
18
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