LMH0346 Datasheet, PDF (4/23 Pages) Texas Instruments – HD/SD SDI Reclocker with Dual Differential Outputs

LMH0346
SNLS248J – APRIL 2007 – REVISED APRIL 2013
www.ti.com
HTSSOP
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
—
—
DAP
WQFN
Pin
24
1
2
3
4
5
6
7
8
9
12
13
14
15
16
17
18
19
20
21
10, 11, 23
22
DAP
PIN DESCRIPTIONS
Name
Description
LF1
LF2
RATE 0
RATE 1
SDI
SDI
V_CC
BYPASS/AUTO BYPASS
OUTPUT MUTE
XTAL IN/EXT CLK
XTAL OUT
LOCK DETECT
SCO/SDO2
SCO/SDO2
V_CCO
SDO
SDO
V_CCO
SD/HD
SCO_EN
V_EE
RSVD
V_EE
Loop Filter.
Loop Filter.
Data Rate select input. This pin has an internal pulldown.
Data Rate select input. This pin has an internal pulldown.
Data Input True.
Data Input Complement.
Positive power supply.
Bypass/Auto Bypass mode select. Bypasses reclocking when high. This
pin has an internal pulldown.
Data and Clock Output Mute Input. Mutes the output when low. This pin
has an internal pullup.
Crystal or External Oscillator Input.
Crystal Oscillator Output.
PLL Lock Detect Output (active high).
Serial Clock or Serial Data Output 2 Complement.
Serial Clock or Serial Data Output 2 True.
Positive power supply (Output Driver).
Data Output Complement.
Data Output True.
Positive power supply (Output Driver).
Data Rate Range Output. Output is high for SD and low for HD or 3G.
Serial Clock or Serial Data 2 Output select. Sets second output to output
the clock when high and the data when low. This pin has an internal
pulldown.
Negative power supply.
Reserved for future use. Do not connect.
Connect exposed DAP to negative power supply (ground).
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
4
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