DS90UB903Q_15 Datasheet, PDF (4/47 Pages) Texas Instruments – 10 - 43MHz 18 Bit Color FPD-Link III Serializer and Deserializer with Bidirectional Control Channel

DS90UB903Q, DS90UB904Q
SNLS332E – JUNE 2010 – REVISED APRIL 2013
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DS90UB903Q SERIALIZER PIN DESCRIPTIONS (continued)
Pin Name
PDB
Pin No.
13
RES
10, 11
FPD-LINK III INTERFACE
DOUT+
17
DOUT-
16
POWER AND GROUND
VDDPLL
14
VDDT
15
VDDCML
18
VDDD
34
VDDIO
31
VSS
DAP
I/O, Type
Description
Input, LVCMOS
w/ pull down
Power down Mode Input Pin.
PDB = H, Serializer is enabled and is ON.
PDB = L, Serailizer is in Power Down mode. When the Serializer is in Power Down,
the PLL is shutdown, and IDD is minimized. Programmed control register data are
NOT retained and reset to default values
Input, LVCMOS Reserved.
w/ pull down This pin MUST be tied LOW.
Input/Output,
CML
Input/Output,
CML
Non-inverting differential output, bidirectional control channel input. The interconnect
must be AC Coupled with a 100 nF capacitor.
Inverting differential output, bidirectional control channel input. The interconnect must
be AC Coupled with a 100 nF capacitor.
Power, Analog
Power, Analog
Power, Analog
Power, Digital
Power, Digital
Ground, DAP
PLL Power, 1.8V ±5%
Tx Analog Power, 1.8V ±5%
CML & Bidirectional Channel Driver Power, 1.8V ±5%
Digital Power, 1.8V ±5%
Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V_DDIO.
V_DDIO can be connected to a 1.8V ±5% or 3.3V ±10%
DAP must be grounded. DAP is the large metal contact at the bottom side, located at
the center of the WQFN package. Connected to the ground plane (GND) with at least
16 vias.
4
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