DS90C385A_15 Datasheet, PDF (4/20 Pages) Texas Instruments – +3.3V Programmable LVDS Transmitter 24-Bit Flat Panel Display Link-87.5 MHz

DS90C385A
SNLS167K – MARCH 2004 – REVISED APRIL 2013
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
LLHT
LVDS Low-to-High Transition Time (Figure 5)
LHLT
LVDS High-to-Low Transition Time (Figure 5)
TPPos0 Transmitter Output Pulse Position (Figure 13)⁽¹⁾
f = 25MHz
-0.45
TPPos1 Transmitter Output Pulse Position
5.26
TPPos2 Transmitter Output Pulse Position
10.98
TPPos3 Transmitter Output Pulse Position
16.69
TPPos4 Transmitter Output Pulse Position
22.41
TPPos5 Transmitter Output Pulse Position
28.12
TPPos6 Transmitter Output Pulse Position
TPPos0 Transmitter Output Pulse Position (Figure 13)⁽¹⁾
f = 40 MHz
33.84
-0.25
TPPos1 Transmitter Output Pulse Position
3.32
TPPos2 Transmitter Output Pulse Position
6.89
TPPos3 Transmitter Output Pulse Position
10.46
TPPos4 Transmitter Output Pulse Position
14.04
TPPos5 Transmitter Output Pulse Position
17.61
TPPos6 Transmitter Output Pulse Position
TPPos0 Transmitter Output Pulse Position (Figure 13)⁽¹⁾
f = 65 MHz
21.18
-0.20
TPPos1 Transmitter Output Pulse Position
2.00
TPPos2 Transmitter Output Pulse Position for Bit 2
4.20
TPPos3 Transmitter Output Pulse Position for Bit 3
6.39
TPPos4 Transmitter Output Pulse Position
8.59
TPPos5 Transmitter Output Pulse Position
10.79
TPPos6 Transmitter Output Pulse Position
TPPos0 Transmitter Output Pulse Position (Figure 13)⁽¹⁾
f = 87.5 MHz
12.99
-0.20
TPPos1 Transmitter Output Pulse Position
1.48
TPPos2 Transmitter Output Pulse Position
3.16
TPPos3 Transmitter Output Pulse Position
4.84
TPPos4 Transmitter Output Pulse Position
6.52
TPPos5 Transmitter Output Pulse Position
8.20
TPPos6 Transmitter Output Pulse Position
9.88
TSTC Required TxIN Setup to TxCLK IN
2.5
(Figure 7) at 85MHz
THTC Required TxIN Hold to TxCLK IN (Figure 7) at 87.5 MHz
0.5
TCCD
TxCLK IN to TxCLK OUT Delay. Measure from TxCLK
IN edge to immediately crossing point of differential
TxCLK OUT by following the positive TxCLK OUT. 50%
duty cycle input clock is assumed. (Figure 8)
T_A = -10°, and
87.5MHz for "Min",
T_A = 70°, and
25MHz for "Max",
V_CC = 3.6V, R_FB
pin = VCC
3.086
Measure from TxCLK IN edge to immediately crossing
point of differential TxCLK OUT by following the positive
TxCLK OUT. 50% duty cycle input clock is assumed.
(Figure 9)
T_A = -10°, and
87.5MHz for "Min",
T_A = 70°, and
25MHz for "Max",
V_CC = 3.6V, R_FB
pin = GND
2.868
Typ
0.75
0.75
0
5.71
11.43
17.14
22.86
28.57
34.29
0
3.57
7.14
10.71
14.29
17.86
21.43
0
2.20
4.40
6.59
8.79
10.99
13.19
0
1.68
3.36
5.04
6.72
8.40
10.08
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Max
Unit
1.4
ns
1.4
ns
+0.45
ns
6.16
ns
11.88
ns
17.59
ns
23.31
ns
29.02
ns
34.74
ns
+0.25
ns
3.82
ns
7.39
ns
10.96
ns
14.54
ns
18.11
ns
21.68
ns
+0.20
ns
2.40
ns
4.60
ns
6.79
ns
8.99
ns
11.19
ns
13.39
ns
+0.20
ns
1.88
ns
3.56
ns
5.24
ns
6.92
ns
8.60
ns
10.28
ns
ns
ns
7.211
ns
6.062
ns
(1) The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature
ranges. This parameter is functionality tested only on Automatic Test Equipment (ATE).
4
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