DRV8313EVM Datasheet, PDF (4/18 Pages) Texas Instruments – DRV8313 TRIPLE HALF-H-BRIDGE DRIVER IC

DRV8313
SLVSBA5A – OCTOBER 2012 – REVISED NOVEMBER 2012
www.ti.com
PIN
NAME
NO.
Output
OUT1
5
OUT2
8
OUT3
9
PGND1
6
PGND2
7
PGND3
10
TYPE
PIN DESCRIPTIONS (continued)
DESCRIPTION
EXTERNAL COMPONENTS OR CONNECTIONS
O
Output 1
O
Output 2
O
Output 3
–
Ground for OUT1
–
Ground for OUT2
–
Ground for OUT3
Connect to loads.
Connect to ground, or to low-side current-sense resistors.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾
Power-supply voltage range (V_M)
Digital-pin voltage range
Comparator input-voltage range
Peak motor-drive output current
Pin voltage (GND1, GND2, GND3)
Continuous motor-drive output current⁽³⁾
T_J
Operating virtual junction temperature range
T_stg
Storage temperature range
VALUE
–0.3 V to 65
–0.5 to 7
–0.5 to 7
Internally limited
±600
2.5
–40 to 150
–60 to 150
UNIT
V
V
V
A
mV
A
ºC
ºC
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal.
(3) Observe power dissipation and thermal limits.
THERMAL INFORMATION
θ_JA
θ_JCtop
θ_JB
ψ_JT
ψ_JB
θ_JCbot
THERMAL METRIC⁽¹⁾
Junction-to-ambient thermal resistance⁽²⁾
Junction-to-case (top) thermal resistance⁽³⁾
Junction-to-board thermal resistance⁽⁴⁾
Junction-to-top characterization parameter⁽⁵⁾
Junction-to-board characterization parameter⁽⁶⁾
Junction-to-case (bottom) thermal resistance⁽⁷⁾
DRV8313
PWP
28 PINS
31.6
15.9
5.6
0.2
5.5
1.4
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA, using a procedure described in JESD51-2a (sections 6 and 7).
(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining θ_JA , using a procedure described in JESD51-2a (sections 6 and 7).
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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