CDCV850DGG Datasheet, PDF (4/20 Pages) Texas Instruments – 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE

CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACE
SCAS647D − OCTOBER 2000 − REVISED APRIL 2013
absolute maximum ratings over operating free-air temperature (unless otherwise noted)^†
Supply voltage range: V_DDQ, AV_DD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V
V_DDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range: V_I (except SCLK and SDATA) (see Notes 1 and 2) . . . . . . . . . –0.5 V to V_DDQ + 0.5 V
V_I (SCLK, SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DDI + 0.5 V
Output voltage range: V_O (except SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . –0.5 V to V_DDQ + 0.5 V
V_O (SDATA) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V_DDQ + 0.5 V
Input clamp current, I_IK (V_I < 0 or V_I > V_DDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Output clamp current, I_OK (V_O < 0 or V_O > V_DDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous output current, I_O (V_O = 0 to V_DDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Package thermal impedance, θ_JA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W
Storage temperature range T_stg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† _{Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and}
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 3.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
TYP
MAX
UNIT
Supply voltage
V_DDQ, AV_DD
2.3
V_DDI (see Note 5)
2.3
CLK, CLK, HCSL Buffer only
0
2.7
V
3.6
0.24
Low level input voltage, V_IL
CLK, CLK
−0.3
FBIN, FBIN
SDATA, SCLK
CLK, CLK, HCSL Buffer only
0.66
0.71
V_DDQ − 0.4
V
V_DDQ/2 − 0.18
0.3 × V_DDI
High level input voltage, V_IH
CLK, CLK
FBIN, FBIN
SDATA, SCLK
DC input signal voltage (see Note 6)
Differential input signal voltage, V_ID (see Note 7)
DC CLK, FBIN
AC CLK, FBIN
Input differential pair cross-voltage, V_IX (see Note 8)
High-level output current, I_OH
Low-level output current, I_OL
SDATA
0.4
V_DDQ/2 + 0.18
0.7 × V_DDI
–0.3
0.36
0.2
0.45×(V_IH−V_IL)
V_DDQ + 0.3
V
V_DDQ + 0.3
V
V_DDQ + 0.6
V
V_DDQ + 0.6
0.55×(V_IH−V_IL)
V
−12 mA
12 V
3 mA
Input slew rate, SR (see Figure 8)
1
4 V/ns
SSC modulation frequency
30
33.3 kHz
SSC clock input frequency deviation
0
−0.50 kHz
Operating free-air temperature, T_A
−40
85 °C
NOTES:
4. Unused inputs must be held high or low to prevent them from floating.
5. All devices on the serial interface bus, with input levels related to V_DDI, must have one common supply line to which the pullup resistor
is connected to.
6. DC input signal voltage specifies the allowable dc execution of differential input.
7. Differential input signal voltage specifies the differential voltage |VTR − VCP| required for switching, where VTR is the true input level
and VCP is the complementary input level.
8. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be
crossing.
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