CDCV850DGG Datasheet, PDF (1/20 Pages) Texas Instruments – 2.5-V PHASE LOCK LOOP CLOCK DRIVER WITH 2-LINE SERIAL INTERFACE

CDCV850
2.5-V PHASE LOCK LOOP CLOCK DRIVER
WITH 2-LINE SERIAL INTERFACE
SCAS647D − OCTOBER 2000 − REVISED APRIL 2013
D Phase-Lock Loop Clock Driver for Double
Data-Rate Synchronous DRAM
DGG PACKAGE
(TOP VIEW)
Applications
D Spread Spectrum Clock Compatible
D Operating Frequency: 60 to 140 MHz
D Low Jitter (cyc−cyc): ±75 ps
D Distributes One Differential Clock Input to
GND 1
Y0 2
Y0 3
V_DDQ 4
Y1 5
48 GND
47 Y5
46 Y5
45 V_DDQ
44 Y6
Ten Differential Outputs
Y1 6
43 Y6
D Two-Line Serial Interface Provides Output
Enable and Functional Control
GND 7
GND 8
42 GND
41 GND
D Outputs Are Put Into a High-Impedance
State When the Input Differential Clocks
Are <20 MHz
D 48-Pin TSSOP Package
D Consumes <250-μA Quiescent Current
D External Feedback Pins (FBIN, FBIN) Are
Used to Synchronize the Outputs to the
Input Clocks
Y2 9
Y2 10
V_DDQ 11
SCLK 12
CLK 13
CLK 14
V_DDI 15
AV_DD 16
AGND 17
40 Y7
39 Y7
38 V_DDQ
37 SDATA
36 FBIN
35 FBIN
34 V_DDQ
33 FBOUT
32 FBOUT
description
GND ¹⁸
Y3 ¹⁹
31 _GND
30 _Y8
The CDCV850 is a high-performance, low-skew,
low-jitter zero delay buffer that distributes a
differential clock input pair (CLK, CLK) to ten
differential pairs of clock outputs (Y[0:9], Y[0:9])
and one differential pair of feedback clock outputs
Y3 ²⁰
V_DDQ ²¹
Y4 ²²
Y4 ²³
GND ²⁴
29 _Y8
28 _VDDQ
27 _Y9
26 _Y9
25 _GND
(FBOUT, FBOUT). The clock outputs are con-
trolled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), the 2-line serial interface (SDATA,
SCLK), and the analog power input (AV_DD). A two-line serial interface can put the individual output clock pairs
in a high-impedance state. When the AV_DD terminal is tied to GND, the PLL is turned off and bypassed for test
purposes.
The device provides a standard mode (100 Kbits/s) 2-line serial interface for device control. The implementation
is as a slave/receiver. The device address is specified in the 2-line serial device address table. Both of the 2-line
serial inputs (SDATA and SCLK) provide integrated pullup resistors (typically 100 kΩ).
Two 8-bit, 2-line serial registers provide individual enable control for each output pair. All outputs default to
enabled at powerup. Each output pair can be placed in a high-impedance mode, when a low-level control bit
is written to the control register. The registers must be accessed in sequential order (i.e., random access of the
registers not supported). The serial interface circuit can be supplied with either 2.5 V or 3.3 V (at VDDI) in
applications where this programming option is not required (after power up, all output pairs will then be enabled).
When the input frequency falls below a suggested detection frequency that is below 20 MHz (typically 10 MHz),
the output pairs are put into a high-impedance condition, the PLL is shut down, and the device will enter a low
power mode. The CDCV850 is also able to track spread spectrum clocking for reduced EMI.
Since the CDCV850 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL.
This stabilization time is required following power up, as well as changes to various 2-line serial registers that
affect the PLL. The CDCV850 is characterized in a temperature range from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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