CD74HC00M96G4 Datasheet, PDF (4/15 Pages) Texas Instruments – High-Speed CMOS Logic Quad 2-Input NAND Gate

CD54HC00, CD74HC00, CD54HCT00, CD74HCT00
DC Electrical Specifications (Continued)
PARAMETER
Quiescent Device
Current
TEST
CONDITIONS
25^oC
SYMBOL V_I (V) I_O (mA) V_CC (V) MIN
I_CC
V_CC or
0
GND
6
-
TYP MAX
-
2
-40^oC TO 85^oC
MIN MAX
-
20
HCT TYPES
High Level Input
Voltage
V_IH
-
-
4.5 to 2
-
-
2
-
5.5
Low Level Input
Voltage
V_IL
-
-
4.5 to -
- 0.8
-
0.8
5.5
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
V_OH
V_IH or - 0.02
4.5
4.4
-
-
4.4
-
V_IL
-4
4.5 3.98 -
-
3.84
-
Low Level Output
V_OL
V_IH or 0.02
4.5
-
- 0.1
-
0.1
Voltage CMOS Loads
V_IL
Low Level Output
Voltage
TTL Loads
4
4.5
-
- 0.26
-
0.33
Input Leakage
Current
I_I
V_CC
-
5.5
-
and
GND
±0.1
-
±1
Quiescent Device
Current
I_CC
V_CC or
0
5.5
-
-
2
-
20
GND
Additional Quiescent
∆I_CC
V_CC
-
4.5 to - 100 360
-
450
Device Current Per
(Note 2) - 2.1
5.5
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theorectical worst case (V_I = 2.4V, V_CC = 5.5V) specification is 1.8mA.
-55^oC TO 125^oC
MIN MAX UNITS
-
40
µA
2
-
V
-
0.8
V
4.4
-
V
3.7
-
V
-
0.1
V
-
0.4
V
-
±1
µA
-
40
µA
-
490
µA
HCT Input Loading Table
INPUT
UNIT LOADS
nA
1.8
nB
1.1
NOTE: Unit Load is ∆I_CC limit
tions table, e.g. 360µA max at
specified
25^oC.
in
DC
Electrical
Specifica-
Switching Specifications Input t_r, t_f = 6ns
PARAMETER
TEST
V_CC
25^oC
-40^oC TO 85^oC -55^oC TO 125^oC
SYMBOL CONDITIONS (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
Propagation Delay,
Input to Output (Figure 1)
t_PLH, t_PHL C_L = 50pF
2
-
- 90
-
115
-
135
ns
4.5 -
-
18
-
23
-
27
ns
6
-
- 15
-
20
-
23
ns
Propagation Delay, Data Input to t_PLH, t_PHL C_L = 15pF
5
-7
-
-
-
-
-
pF
Output Y
4