CD74HC00M96G4 Datasheet, PDF (1/15 Pages) Texas Instruments – High-Speed CMOS Logic Quad 2-Input NAND Gate

Data sheet acquired from Harris Semiconductor
SCHS116C
January 1998 - Revised September 2003
CD54HC00, CD74HC00,
CD54HCT00, CD74HCT00
High-Speed CMOS Logic
Quad 2-Input NAND Gate
[ /Title
(CD54
HC00,
CD54
HCT00
,
CD74
HC00,
CD74
HCT00
)
/Sub-
Features
Description
• Buffered Inputs
•
Typical Propagation Delay:
C_L = 15pF, T_A = 25^oC
7ns
at
V_CC
=
5V,
• Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55^oC to 125^oC
The CD54HC00, CD74HC00, CD54HCT00, and
CD74HCT00 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The 74HCT logic family is functionally pin
compatible with the standard 74LS logic family.
Ordering Information
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• Alternate Source is Philips/Signetics
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N_IL = 30%, N_IH = 30% of V_CC
at V_CC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V_IL= 0.8V (Max), V_IH = 2V (Min)
- CMOS Input Compatibility, I_l ≤ 1µA at V_OL, V_OH
PART NUMBER
TEMP. RANGE
(^oC)
PACKAGE
CD54HC00F3A
-55 to 125
14 Ld CERDIP
CD54HCT00F3A
-55 to 125
14 Ld CERDIP
CD74HC00E
-55 to 125
14 Ld PDIP
CD74HC00M
-55 to 125
14 Ld SOIC
CD74HC00MT
-55 to 125
14 Ld SOIC
CD74HC00M96
-55 to 125
14 Ld SOIC
CD74HCT00E
-55 to 125
14 Ld PDIP
CD74HCT00M
-55 to 125
14 Ld SOIC
CD74HCT00MT
-55 to 125
14 Ld SOIC
CD74HCT00M96
-55 to 125
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC00, CD54HCT00,
(CERDIP)
CD74HC00, CD74HCT00
(PDIP, SOIC)
TOP VIEW
1A 1
1B 2
1Y 3
2A 4
2B 5
2Y 6
GND 7
14 V_CC
13 4B
12 4A
11 4Y
10 3B
9 3A
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2003, Texas Instruments Incorporated
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