CD4069UB_16 Datasheet, PDF (4/30 Pages) Texas Instruments – CMOS Hex Inverter

CD4069UB
SCHS054D – NOVEMBER 1998 – REVISED FEBRUARY 2016
6 Specifications
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6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)⁽¹⁾
V_DD DC supply-voltage (voltages referenced to V_SS terminal)
V_I
Input voltage, all inputs
I_IK
DC input current, any one input
Power dissipation per package
P_D
–55°C to 100°C
100°C to 125°C
Device dissipation per output transistor
Full range (all package types)
Lead temperature⁽²⁾
T_J
Junction temperature
T_stg Storage temperature
MIN
–0.5
–0.5 to V_DD
–10
12
–65
MAX
20
0.5
10
500
200
100
265
150
150
UNIT
V
V
mA
mW
mW
°C
°C
°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) During soldering at distance 1/16 inch ± 1/32 inch (1.59 mm ± 0.79 mm) from case for 10 s maximum
6.2 ESD Ratings
V_(ESD) Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾
Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾
VALUE
±500
±200
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
UNIT
V
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
V_DD
Supply voltage
T_A
Operating temperature
MIN
MAX
UNIT
3
18
V
–55
125
°C
6.4 Thermal Information
THERMAL METRIC⁽¹⁾
D (SOIC)
J (CDIP)
CD4069UB
N (PDIP) NS (SO)
PW (TSSOP) UNIT
14 PINS 14 PINS 14 PINS
14 PINS
14 PINS
R_θJA
Junction-to-ambient thermal resistance
94.9
—
57.9
91.2
R_θJC(top) Junction-to-case (top) thermal resistance
56.4
28.5
45.5
48.8
R_θJB
Junction-to-board thermal resistance
49.2
—
37.7
50
ψ_JT
Junction-to-top characterization parameter
21.1
—
30.6
15
ψ_JB
Junction-to-board characterization parameter
48.9
—
37.6
49.6
R_θJC(bot) Junction-to-case (bottom) thermal resistance
N/A
N/A
N/A
N/A
122.1
50.8
63.8
6.3
63.3
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4
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