CD4069UB_16 Datasheet, PDF (16/30 Pages) Texas Instruments – CMOS Hex Inverter

CD4069UB
SCHS054D – NOVEMBER 1998 – REVISED FEBRUARY 2016
www.ti.com
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in
Recommended Operating Conditions.
Each V_CC pin must have a good bypass capacitor to prevent power disturbance. For devices with a single supply,
TI recommends a 0.1-μF capacitor. If there are multiple V_CC pins, then TI recommends a 0.01-μF or 0.022-μF
capacitor for each power pin. It is acceptable to parallel multiple bypass capacitors to reject different frequencies
of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor must be installed as
close to the power pin as possible for best results.
11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs must never float.
In many cases, digital logic device functions or parts of these functions are unused (for example, when only two
inputs of a triple-input and gate are used, or only 3 of the 4 buffer gates are used). Such input pins must not be
left unconnected because the undefined voltages at the outside connections result in undefined operational
states. This rule must be observed under all circumstances specified in the next paragraph.
All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating.
See the application note, Implications of Slow or Floating CMOS Inputs (SCBA004), for more information on the
effects of floating inputs. The logic level must apply to any particular unused input depending on the function of
the device. Generally, they are tied to GND or V_CC (whichever is convenient).
11.2 Layout Example
V_CC
Unused Input
Input
Output
Input
Unused Input
Output
16
Submit Documentation Feedback
Product Folder Links: CD4069UB
Copyright © 1998–2016, Texas Instruments Incorporated