BQ4850Y_14 Datasheet, PDF (4/17 Pages) Texas Instruments – RTC Module With 512Kx8 NVSRAM

Not Recommended For New Designs
bq4850Y
Memory Interface
Read Mode
The bq4850Y is in read mode whenever OE (output en-
able) is low and CE (chip enable) is low. The device ar-
chitecture allows ripple-through access of data from
eight of 4,194,304 locations in the static storage array.
Thus, the unique address specified by the 19 address in-
puts defines which one of the 524,288 bytes of data is to
be accessed. Valid data is available at the data I/O pins
within tAA (address access time) after the last address
input signal is stable, providing that the CE and OE
(output enable) access times are also satisfied. If the CE
and OE access times are not met, valid data is available
after the latter of chip enable access time (tACE) or out-
put enable access time (tOE).
CE and OE control the state of the eight three-state
data I/O signals. If the outputs are activated before tAA,
the data lines are driven to an indeterminate state until
tAA. If the address inputs are changed while CE and OE
remain low, output data remains valid for tOH (output
data hold time), but goes indeterminate until the next
address access.
Write Mode
The bq4850Y is in write mode whenever WE and CE are
active. The start of a write is referenced from the
latter-occurring falling edge of WE or CE. A write is ter-
minated by the earlier rising edge of WE or CE. The ad-
dresses must be held valid throughout the cycle. CE or
WE must return high for a minimum of tWR2 from CE or
tWR1 from WE prior to the initiation of another read or
write cycle.
Data-in must be valid tDW prior to the end of write and
remain valid for tDH1 or tDH2 afterward. OE should be
kept high during write cycles to avoid bus contention; al-
though, if the output bus has been activated by a low on
CE and OE, a low on WE disables the outputs tWZ after
WE falls.
Data-Retention Mode
With valid VCC applied, the bq4850Y operates as a
conventional static RAM. Should the supply voltage
decay, the RAM automatically power-fail deselects,
write-protecting itself tWPT after VCC falls below VPFD.
All outputs become high impedance, and all inputs are
treated as “don’t care.”
If power-fail detection occurs during a valid access, the
memory cycle continues to completion. If the memory
cycle fails to terminate within time tWPT, write-
protection takes place. When VCC drops below VSO, the
control circuit switches power to the internal energy
source, which preserves data.
The internal coin cell maintains data in the bq4850Y af-
ter the initial application of VCC for an accumulated pe-
riod of at least 10 years when VCC is less than VSO. As
system power returns and Vcc rises above VSO, the bat-
tery is disconnected, and the power supply is switched to
external VCC. Write-protection continues for tCER after
VCC reaches VPFD to allow for processor stabilization.
After tCER, normal RAM operation can resume.
Clock Interface
Reading the Clock
The interface to the clock and control registers of the
bq4850Y is the same as that for the general-purpose
storage memory. Once every second, the user-accessible
clock/calendar locations are updated simultaneously
from the internal real time counters. To prevent reading
data in transition, updates to the bq4850Y clock regis-
ters should be halted. Updating is halted by setting the
read bit D6 of the control register to 1. As long as the
read bit is 1, updates to user-accessible clock locations
are inhibited. Once the frozen clock information is re-
trieved by reading the appropriate clock memory loca-
tions, the read bit should be reset to 0 in order to allow
updates to occur from the internal counters. Because the
internal counters are not halted by setting the read bit,
reading the clock locations has no effect on clock accu-
racy. Once the read bit is reset to 0, within one second
the internal registers update the user-accessible regis-
ters with the correct time. A halt command issued dur-
ing a clock update allows the update to occur before
freezing the data.
Setting the Clock
Bit D7 of the control register is the write bit. Like the
read bit, the write bit when set to a 1 halts updates to
the clock/calendar memory locations. Once frozen, the
locations can be written with the desired information in
24-hour BCD format. Resetting the write bit to 0 causes
the written values to be transferred to the internal clock
counters and allows updates to the user-accessible regis-
ters to resume within one second. Use the write bit, D7,
only when updating the time registers (7FFFF–7FFF9).
Stopping and Starting the Clock Oscillator
The OSC bit in the seconds register turns the clock on or
off. If the bq4850Y is to spend a significant period of
time in storage, the clock oscillator can be turned off to
preserve battery capacity. OSC set to 1 stops the clock
oscillator. When OSC is reset to 0, the clock oscillator is
turned on and clock updates to user-accessible memory
locations occur within one second.
The OSC bit is set to 1 when shipped from the Bench-
marq factory.
SLUS057A- January 2005
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