BQ4850Y_14 Datasheet, PDF (10/17 Pages) Texas Instruments – RTC Module With 512Kx8 NVSRAM

Not Recommended For New Designs
bq4850Y
Write Cycle (TA =TOPR _, VCCMIN _≤ VCC ≤ VCCMAX)
Symbol
Parameter
tWC
Write cycle time
tCW
Chip enable to end of write
tAW
Address valid to end of write
tAS
Address setup time
–85
Min. Max.
85
-
75
-
75
-
0
-
Units
ns
ns
ns
ns
Conditions/Notes
(1)
(1)
Measured from address valid to begin-
ning of write. (2)
tWP
Write pulse width
65
tWR1 Write recovery time (write cycle 1)
5
Measured from beginning of write to
-
ns _{end of write. (1)}
Measured from WE going high to end
-
ns _{of write cycle. (3)}
tWR2 Write recovery time (write cycle 2)
15
tDW
Data valid to end of write
35
tDH1
Data hold time (write cycle 1)
0
Measured from CE going high to end of
-
ns _{write cycle. (3)}
Measured to first low-to-high transi-
-
ns _{tion of either CE or WE.}
Measured from WE going high to end
-
ns _{of write cycle. (4)}
tDH2
Data hold time (write cycle 2)
Measured from CE going high to end of
10
-
ns _{write cycle. (4)}
tWZ
Write enabled to output in high Z
0
30
ns I/O pins are in output state. (5)
tOW
Output active from end of write
0
-
ns I/O pins are in output state. (5)
Notes:
1. A write ends at the earlier transition of CE going high and WE going high.
2. A write occurs during the overlap of a low CE and a low WE. A write begins at the later transition
of CE going low and WE going low.
3. Either tWR1 or tWR2 must be met.
4. Either tDH1 or tDH2 must be met.
5. If CE goes low simultaneously with WE going low or after WE going low, the outputs remain in
high-impedance state.
SLUS057A- January 2005
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