BQ24745_14 Datasheet, PDF (4/39 Pages) Texas Instruments – SMBus-Controlled Multi-Chemistry Battery

bq24745
SLUS761D – DECEMBER 2007 – REVISED OCTOBER 2011
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PIN
NO. NAME
1 ICREF
2 ACIN
3 VREF
4 EAO
5 EAI
6 FBO
7 CE
8 VICM
9 SDA
10 SCL
11 VDDSMB
12 GND
13 ACOK
14 NC
15 VFB
16 NC
17 CSON
18 CSOP
19 PGND
20 LGATE
21 VDDP
22 DCIN
23 PHASE
24 UGATE
Table 1. PIN FUNCTIONS – 28-PIN QFN
FUNCTION
Input-current comparator voltage reference input. Connect a resistor divider from VREF to ICREF and from ICREF to
GND to program the reference for the ICOUT comparator. The ICREF pin voltage is compared to the VICM pin
voltage and the logic output is given on the ICOUT open-drain pin. Connecting a positive feedback resistor from the
ICREF pin to the ICOUT pin programs the hysteresis.
Adapter-detected voltage-set input. Program the adapter-detect threshold by connecting a resistor divider from the
adapter input to ACIN pin to GND. Adapter voltage is detected if the ACIN-pin voltage is greater than 2.4 V. The VICM
current-sense amplifier, ICOUT comparator, and ACOK output are active when the ACIN pin voltage is greater than
0.6 V.
3.3-V regulated voltage output. Place a 1-μF ceramic capacitor from VREF to the GND pin close to the IC. This
voltage could be used for ratiometric programming of voltage and current regulation and for programming the ICREF
threshold.
Error amplifier output for compensation. Connect the feedback-compensation components from EAO to EAI. Typically,
a capacitor in parallel with a series resistor and capacitor. This node is internally compared to the PWM sawtooth
oscillator signal.
Error amplifier input for compensation. Connect the feedback compensation components from EAI to EAO. Connect
the input compensation from FBO to EAI.
Feedback output for compensation. Connect the input compensation from FBO to EAI. Typically, a resistor in parallel
with a series resistor and capacitor.
Charge enable active-high logic input. HI enables charge. LO disables charge.
Adapter current-sense-amplifier output. The VICM voltage is 20 times the differential voltage across CSSP-CSSN.
Place a 100-pF (max) or less ceramic decoupling capacitor from VICM to GND.
SMBus data input. Connect to the SMBus data line from the host controller. A 10-kΩ pullup resistor to the host
controller power rail is needed.
SMBus clock input. Connect to the SMBus clock line from the host controller. A 10-kΩ pullup resistor to the host
controller power rail is needed.
Input voltage for SMBus logic. Connect a 3.3-V supply rail or 5-V rail to the VDDSMB pin. Connect a 0.1-μF ceramic
capacitor from VDDSMB to GND for decoupling.
Analog ground. On PCB layout, connect to the analog ground plane, and only connect to PGND through the thermal
pad underneath the IC.
Valid adapter active-high detect logic open-drain output. Pulled HI when Input voltage is above the ACIN programmed
threshold. Connect a 10-kΩ pullup resistor from the ACOK pin to pull up the supply rail.
No connect. Pin floating internally.
Battery-voltage remote sense. Directly connect a Kelvin sense trace from the battery-pack positive terminal to the VFB
pin to sense the battery pack voltage accurately. Place a 0.1-μF capacitor from VFB to GND close to the IC to filter
high-frequency noise.
No Connect. Pin floating internally.
Charge-current sense resistor, negative input. An optional 0.1-μF ceramic capacitor is placed from the CSON pin to
GND for common-mode filtering. A 0.1-μF ceramic capacitor is placed from CSON to CSOP to provide
differential-mode filtering.
Charge-current sense resistor, positive input. A 0.1-μF ceramic capacitor is placed from CSOP pin to GND for
common-mode filtering. A 0.1-μF ceramic capacitor is placed from CSON to CSOP to provide differential-mode
filtering.
Power ground. On PCB layout, connect directly to the source of the low-side power MOSFET, and to the to ground
connection of the input and output capacitors of the charger. Only connect to GND through the thermal pad
underneath the IC.
PWM low-side driver output. Connect to the gate of the low-side power MOSFET with a short trace.
PWM low-side driver positive 6-V supply output. Connect a 1-μF ceramic capacitor from VDDP to the PGND pin, close
to the IC. Use for high-side driver bootstrap voltage by connecting a small signal Schottky diode from VDDP to BOOT.
IC-power positive supply. Connect to the common-source (diode-OR) point: source of high-side P-channel MOSFET
and source of reverse blocking power P-channel MOSFET. Place a 1-μF ceramic capacitor from DCIN to the GND pin
close to the IC. Place a 10-Ω resistor from the adapter input to the DCIN pin to limit inrush current.
PWM high-side driver negative supply. Connect to the phase-switching node (junction of the low-side power MOSFET
drain, high-side power MOSFET source, and output inductor). Connect the 0.1-μF bootstrap capacitor from PHASE to
BOOT.
PWM high-side driver output. Connect to the gate of the high-side power MOSFET with a short trace.
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