DLPC200_17 Datasheet, PDF (39/52 Pages) Texas Instruments – DLP Digital Controller for the DLP5500 DMD

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DLPC200
DLPS014E – APRIL 2010 – REVISED AUGUST 2014
Typical Application (continued)
8.2.2 Detailed Design Procedure
8.2.2.1 DLPC200 System Interfaces
The DLPC200 supports the following interfaces: extended display identification data (EDID), USB, SPI, parallel
flash, serial flash, DDR2 SDRAM, and two RGB888 input ports, which are described in the following subsections.
8.2.2.1.1 DLPC200 Master, I²C Interface for EDID Programming
The DLPC200 controller I²C interface is only used to program the HDMI EDID. Upon plugging in an HDMI
source, the DMD resolution is compared to the HDMI output resolution programmed in the HDMI EDID PROM. If
the two resolutions do not match, then the HDMI EDID is adjusted to match the DMD resolution.
The bidirectional I²C bus consists of the serial clock (SCL) and serial data (SDA) lines. Both lines must be
connected to a positive supply through a pullup resistor when connected to the output stages of a device. Data
transfer may be initiated only when the bus is not busy.
I²C communication with this device is initiated by a master sending a Start condition, a high-to-low transition on
the SDA input/output while the SCL input is high. After the Start condition, the device address byte is sent, MSB
first, including the data direction bit (R/W).
After receiving the valid address byte, this device responds with an ACK, a low on the SDA input/output during
the high of the ACK-related clock pulse.
On the I²C bus, only one data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the high pulse of the clock period, as changes in the data line at this time are interpreted as control
commands (Start or Stop). A Stop condition (a low-to-high transition on the SDA input/output while the SCL input
is high) is sent by the master.
Any number of data bytes can be transferred from the transmitter to the receiver between the Start and Stop
conditions. Each byte of eight bits is followed by one ACK bit. The transmitter must release the SDA line before
the receiver can send an ACK bit. The device that acknowledges must pull down the SDA line during the ACK
clock pulse so that the SDA line is stable low during the high pulse of the ACK-related clock period. Setup and
hold times must be met to ensure proper operation.
Table 2. Recommended EDID PROM Devices
PART NUMBER
24LC02B
MANUFACTURER
Microchip Technology
8.2.2.1.2 USB Interface
The USB interface consists of a single-chip integrated USB 2.0 transceiver, smart SIE, and enhanced 8051
microprocessor running at 48 MHz (nominal) that supports USB 2.0.
8.2.2.1.3 Bus Protocol
USB is a polled bus. The host controller (typically at PC) initiates all data transfers. Each transaction begins
when the PC sends a packet. Communications are always through the bulk transfer mode, and 512 bytes of data
are always written/read at a time. The packet consists of the following:
• Header (6 bytes)
• Data (505 bytes)
• Checksum (1 byte)
The USB device that is addressed selects itself by decoding the appropriate address fields. The direction of data
transfer, either read or write, is specified in the packet header. The source of the transaction then sends a data
packet or indicates it has no data to transfer. At the end of either a single packet transfer or a multi-packet
transfer, the destination responds with a handshake packet indicating whether the transfer was successful.
The packet header consists of:
• CMD1 – Indicates if packet is write/write response or read/read response
• CMD2 – Groups major functions together
• CMD3 – Provides more information about packet grouping defined in CMD2
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