AVCE6467T-3 Datasheet, PDF (39/352 Pages) Texas Instruments – VCE6467T, AVCE6467T Digital Media System-on-Chip

VCE6467T, AVCE6467T
www.ti.com
SPRS690 – MARCH 2011
Table 2-10. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL
NAME
PCI_AD15/
HD15/EM_D15
PCI_AD14/
HD14 /EM_D14
PCI_AD13/
HD13/EM_D13
PCI_AD12/
HD12/EM_D12
PCI_AD11/
HD11/EM_D11
PCI_AD10/
HD10/EM_D10
PCI_AD9/
HD9/EM_D9
PCI_AD8/
HD8/EM_D8
PCI_AD7/
HD7/EM_D7
PCI_AD6/
HD6/EM_D6
PCI_AD5/
HD5/EM_D5
PCI_AD4/
HD4/EM_D4
PCI_AD3/
HD3/EM_D3
PCI_AD2/
HD2/EM_D2
PCI_AD1/
HD1/EM_D1
PCI_AD0/
HD0/EM_D0
PCI_IRDY/
HRDY/
EM_A[17]/(CLE)
PCI_TRDY/
HHWIL/
EM_A[16]/(ALE)
PCI_INTA/
EM_WAIT2/
(RDY2/BSY2)
IORDY/
GP[21]/EM_WAIT3/
(RDY3/BSY3)
DIOW/
GP[20]/EM_WAIT4/
(RDY4/BSY4)
DIOR/
GP[19]/EM_WAIT5/
(RDY5/BSY5)
PCI_SERR/
HDS1/
EM_OE
TYPE ⁽¹⁾ OTHER^{(2) (3)}
NO.
DESCRIPTION
E5 I/O/Z
C1 I/O/Z
E4 I/O/Z
D3 I/O/Z
E3 I/O/Z
D2 I/O/Z
F5 I/O/Z
D1 I/O/Z
E2 I/O/Z
F3 I/O/Z
E1 I/O/Z
G5 I/O/Z
F2 I/O/Z
G4 I/O/Z
F1 I/O/Z
G3 I/O/Z
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
These pins are multiplexed between PCI, HPI, and EMIFA.
For EMIFA mode, these pins are the 16-bit bidirectional data bus (EM_D[15:0])
[I/O/Z].
When EMIFA is configured for an 8-bit asynchronous memory, only EM_D[7:0]
pins are used.
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
IPD
DV_DD33
EMIFA FUNCTIONAL PINS: NAND
A3 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is address bit 17 output EM_A[17] (O/Z).
When used for EMIFA (NAND), this pin is Command Latch Enable output (CLE).
E6 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
For EMIFA, this pin is address bit 16 output EM_A[16] (O/Z).
When used for EMIFA (NAND), this pin is Address Latch Enable output (ALE).
C11 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI and EMIFA.
In EMIFA mode, this pin is wait state extension input 2 EM_WAIT2 (I).
When used for EMIFA (NAND), this pin is the ready/busy 2 input (RDY2/BSY2).
D11 I/O/Z
IPU
DV_DD33
This pin is multiplexed between ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is wait state extension input 3 EM_WAIT3 (I).
When used for EMIFA (NAND), this pin is the ready/busy 3 input (RDY3/BSY3).
A11 I/O/Z
IPU
DV_DD33
This pin is multiplexed between ATA, GPIO, and EMIFA.
In EMIFA mode, this pin is wait state extension input 4 EM_WAIT4 (I).
When used for EMIFA (NAND), this pin is the ready/busy 4 input (RDY4/BSY4).
E10 I/O/Z
IPU
DV_DD33
This pin is multiplexed between ATA, GPIO, and EMIFA.
For EMIFA, this pin is wait state extension input 5 EM_WAIT5 (I).
When used for EMIFA (NAND), this pin is the ready/busy 5 input (RDY5/BSY5).
B2 I/O/Z
IPU
DV_DD33
This pin is multiplexed between PCI, HPI, and EMIFA.
In EMIFA mode, this pin is the output enable output EM_OE (O/Z).
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