ADS8691 Datasheet, PDF (39/73 Pages) Texas Instruments – 18-Bit, High-Speed, Single-Supply, SAR ADC Data Acquisition System with Programmable, Bipolar Input Ranges

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ADS8691, ADS8695, ADS8699
SBAS777 – DECEMBER 2016
7.5 Programming
The device features nine configuration registers (as described in the Register Maps section) and supports two
types of data transfer operations: data write (the host configures the device), and data read (the host reads data
from the device).
7.5.1 Data Transfer Frame
A data transfer frame between the device and the host controller begins at the falling edge of the CONVST/CS
pin and ends when the device starts conversion at the subsequent rising edge. The host controller can initiate a
data transfer frame by bringing the CONVST/CS signal low (as shown in Figure 75) after the end of the CONV
phase, as described in the CONV State section.
CONVST/CS
Frame F
RVS
SCLK
SDI
SDO-x
As per output protocol selection.
N SCLKs
Valid Command
Data Output or OSR Contents
td_RVS
SCLK Counter
0
Output Data Word
D31
D0
SCLK Counter
N
Input Shift Register (ISR)
B31
B0
D31
D0
Output Shift Register (OSR)
B31
B0
Command Processor
Figure 75. Data Transfer Frame
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