ADC31JB68 Datasheet, PDF (39/74 Pages) Texas Instruments – Single Channel 16-bit 500 Msps Analog to Digital Converter

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ADC31JB68
SLASE60A – SEPTEMBER 2015 – REVISED SEPTEMBER 2015
8.5.1.14 DC_MODE (DC Offset Correction Mode) (address = 0x003D) [reset = 0x00]
Figure 51. DC_MODE (DC Offset Correction Mode)
7
6
5
4
3
Reserved
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
2
1
TC_DC[1:0]
R/W
0
DC_EN
R/W
Table 19. DC_MODE (DC Offset Correction Mode)
Bit
Field
7:3
Reserved
2:1
TC_DC[1:0]
0
DC_EN
Type
R/W
R/W
Reset
00000
00
R/W
0
Description
Reserved and must be written as 00000.
DC offset filter time constant.
The time constant determines the filter bandwidth of the DC high-pass
filter.
TC_TD
00
01
10
11
Time Constant
(F_S = 500 MSPS)
8.6 µs
65 µs
526 µs
4.2 ms
3-dB Bandwidth
(F_S = 500 MSPS)
18.5 kHz
2.45 kHz
303 Hz
38 Hz
3-dB Bandwidth
(Normalized)
37e^–6 × Fs
4.9e^–6 × Fs
605e^–9 × Fs
76e^–9 × Fs
DC offset correction enable
0 : Disable DC offset correction
1 : Enable DC offset correction
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