TAS5780M Datasheet, PDF (38/204 Pages) Texas Instruments – Digital Input, Closed-Loop Class-D Amplifier with 96-kHz Processing

TAS5780M
SLASEG7 – DECEMBER 2016
www.ti.com
Table 5. PLL Configuration Recommendations
EQUATIONS DESCRIPTION
f_S (kHz)
R_MCLK
MCLK (MHz)
Sampling frequency
Ratio between sampling frequency and MCLK frequency (MCLK frequency = RMCLK x sampling frequency)
System master clock frequency at MCLK input (pin 20)
PLL VCO (MHz) PLL VCO frequency as PLLCK in Figure 58
P
One of the PLL coefficients in Equation 1
PLL REF (MHz) Internal reference clock frequency which is produced by MCLK / P
M=K×R
The final PLL multiplication factor computed from K and R as described in Equation 1
K = J.D
One of the PLL coefficients in Equation 1
R
One of the PLL coefficients in Equation 1
PLL f_S
DSP f_S
NMAC
Ratio between f_S and PLL VCO frequency (PLL VCO / f_S)
Ratio between operating clock rate and f_S (PLL f_S / NMAC)
The clock divider value in Table 3
DSP CLK (MHz) The operating frequency as DSPCK in Figure 58
MOD f_S
MOD f (kHz)
Ratio between DAC operating clock frequency and f_S (PLL f_S / NDAC)
DAC operating frequency as DACCK in
NDAC
DAC clock divider value in Table 3
DOSR
OSR clock divider value in Table 3 for generating OSRCK in Figure 58. DOSR must be chosen so that MOD f_S / DOSR =
16 for correct operation.
NCP
NCP (negative charge pump) clock divider value in Table 3
CP f
% Error
Negative charge pump clock frequency (f_S × MOD f_S / NCP)
Percentage of error between PLL VCO / PLL f_S and f_S (mismatch error).
• This value is typically zero but can be non-zero especially when K is not an integer (D is not zero).
• This value can be non-zero only when the TAS5780M device acts as a master.
The previous equations explain how to calculate all necessary coefficients and controls to configure the PLL.
Table 6 provides for easy reference to the recommended clock divider settings for the PLL as a Master Clock.
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