BQ27520-G2 Datasheet, PDF (38/47 Pages) Texas Instruments – System-Side Impedance Track™ Fuel Gauge With Integrated LDO

bq27520-G2
SLUSAB7A – MARCH 2011 – REVISED AUGUST 2011
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7.2 I²C Time Out
The I²C engine will release both SDA and SCL if the I²C bus is held low for the time defined by I²C
Timeout times 0.5 second. If the bq27520-G2 was holding the lines, releasing them will free for the
master to drive the lines. If an external condition is holding either of the lines low, the I²C engine will enter
the low power sleep mode.
7.3 I²C Command Waiting Time
To make sure the correct results of a command with the 400KHz I²C operation, a proper waiting time
should be added between issuing command and reading results. For subcommands, the following
diagram shows the waiting time required between issuing the control command the reading the status with
the exception of checksum and OCV commands. A 100ms waiting time is required between the checksum
command and reading result, and a 1.2 second waiting time is required between the OCV command and
result. For read-write standard command, a minimum of 2 seconds is required to get the result updated.
For read-only standard commands, there is no waiting time required, but the host should not issue all
standard commands more than two times per second. Otherwise, the gauge could result in a reset issue
due to the expiration of the watchdog timer.
S ADDR [6:0] 0 A
S ADDR [6:0] 0 A
CMD [7:0]
CMD [7:0]
A DATA [7:0] A DATA [7:0] A P 66ms
A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0]
Waiting time between control subcommand and reading results
N P 66ms
S ADDR [6:0] 0 A CMD [7:0] A Sr ADDR [6:0] 1 A DATA [7:0] A DATA [7:0] A
DATA [7:0] A DATA [7:0] N P 66ms
Waiting time between continuous reading results
7.4 I²C Clock Stretching
I²C clock stretches can occur during all modes of fuel gauge operation. In the SLEEP and HIBERNATE
modes, a short clock stretch will occur on all I2C traffic as the device must wake-up to process the packet.
In NORMAL and SLEEP+ modes, clock stretching will only occur for packets addressed for the fuel
gauge. The timing of stretches will vary as interactions between the communicating host and the gauge
are asynchronous. The I²C clock stretches may occur after start bits, the ACK/NAK bit and first data bit
transmit on a host read cycle. The majority of clock stretch periods are small (<= 4mSec) as the I2C
interface peripheral and CPU firmware perform normal data flow control. However, less frequent but more
significant clock stretch periods may occur when data flash (DF) is being written by the CPU to update the
resistance (Ra) tables and other DF parameters such as Qmax. Due to the organization of DF, updates
need to be written in data blocks consisting of multiple data bytes.
An Ra table update requires erasing a single page of DF, programming the updated Ra table and a flag.
The potential I²C clock stretching time is 24ms max. This includes 20ms page erase and 2ms row
programming time (x2 rows). The Ra table updates occur during the discharge cycle and at up to 15
resistance grid points that occur during the discharge cycle.
A DF block write typically requires a max of 72ms. This includes copying data to a temporary buffer and
updating DF. This temporary buffer mechanism is used to protect from power failure during a DF update.
The first part of the update requires 20ms time to erase the copy buffer page, 6 ms time to write the data
into the copy buffer and the program progress indicator (2ms for each individual write). The second part of
the update is writing to the DF and requires 44ms DF block update time. This includes a 20ms each page
erase for two pages and 2ms each row write for two rows.
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COMMUNICATIONS
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