ADS8363_14 Datasheet, PDF (38/50 Pages) Texas Instruments – Dual, 1MSPS, 16-/14-/12-Bit, 4×2 or 2×2 Channel, Simultaneous Sampling Analog-to-Digital Converter

ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
SDI versus A0
Pin 18 (SDI) of the ADS8363/7263/7223 is used to
update the internal registers, whereas on the
ADS8361, pin 18 (A0) is used in conjunction with M0
to select the input channel.
If, in an existing design, the ADS8361 is used in
two-channel mode (M0 = '0') and the status of the A0
pin is unchanged within the first four clock cycles
after issuing a conversion start (rising edge of
CONVST), the ADS8363/7263/7223 act similarly to
the ADS8361 and convert either channels CHx0 (if
SDI is held low during the entire period) or channels
CHx1 (if SDI is held high during the entire period).
Figure 37 shows the behavior of the
ADS8363/7263/7223 in such a situation.
The ADS8363/7263/7223 can be also be used to
replace the ADS8361 when run in four-channel mode
(M0 = '1'). In this case, the A0 pin is held static (high
or low), which is also required in for the SDI pin to
prevent accidental update of the SDI register.
In both cases described above, the additional
features
of
the
ADS8363/7263/7223
(pseudo-differential input mode, programmable
reference voltage output, and the various
power-down modes) cannot be accessed, but the
hardware and software would remain
backward-compatible to the ADS8361.
Internal Reference
The internal reference of the ADS8361 delivers 2.5V
(typ) after power up, while the reference output of the
ADS8363/7263/7223 is powered down by default. In
this case, the unbuffered reference input has a
code-dependent input impedance, while the
ADS8361 offers a high-impedance (buffered)
reference input. If an existing ADS8361-based design
uses the internal reference of the device and relies on
an external resistor divider to adjust the input voltage
range of the ADC, migration to the ADS8363 family
requires one of the following conditions:
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• A software change to setup internal reference
DAC1 properly through SDI while removing the
external resistors; or
• An additional external buffer between the resistor
divider and the required 22µF (min) capacitor on
the REFIO1 input.
In the latter case, while the capacitor stabilizes the
reference voltage during the entire conversion, the
buffer must recharge it by providing an average
current only; thus, the required minimum bandwidth of
the buffer can be calculated using Equation 4:
f_-3dB =
ln(2) × 2
2p × 20t_CLK
(4)
The buffer must also be capable of driving the 22µF
load while maintaining its stability.
Timing
In half-clock mode (default), the ADS8363/7263/7223
family of devices provides the conversion delay after
completion of the conversion (see Figure 1), while the
ADS8361 offers the conversion result during the
conversion process.
RD
The ADS8363/7263/7223 output the first bit with the
falling edge of the RD input. The ADS8361 starts the
data transfer with the first falling edge of the clock if
RD is high.
If the ADS8363/7263/7223 operate with half-clock
timing in modes II and IV, the RD input should not be
held high longer than one clock cycle to ensure
proper function of the data output SDOA.
CONVST
If the ADS8363/7263/7223 operate with half-clock
timing in modes II and IV, the CONVST input must
not be held high longer than one clock cycle to
ensure proper function of the device.
38
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