ADS8363_14 Datasheet, PDF (31/50 Pages) Texas Instruments – Dual, 1MSPS, 16-/14-/12-Bit, 4×2 or 2×2 Channel, Simultaneous Sampling Analog-to-Digital Converter

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Special Read Mode II (Half-Clock Mode Only)
For Mode II, a special read mode is available in the
ADS8363/7263/7223 where both data results can be
read out triggered by a single RD pulse (refer to
Figure 36). To activate this mode, The SR bit in the
CONFIG register must be set to '1' (see Table 6). The
CONVST and RD pins can still be tied together but
are issued every 40 CLOCK cycles instead of 20.
Output data are presented on SDOA only while
SDOB is held in 3-state.
20
20
1
1
1
CLOCK
ADS8363
ADS7263
ADS7223
SBAS523B – OCTOBER 2010 – REVISED JANUARY 2011
The RD signal in this mode must not be longer than
one clock cycle to avoid corruption of output data.
This special mode can be used for fully- or
pseudo-differential inputs. Channel information is
valid in fully-differential mode only if CID = '0' (it
contains correct ADC information while the channel
bit is invalid in pseudo-differential mode). Note that
FIFO is not available in this mode.
20
20
20
1
1
1
SDI
CONVST
and RD
C[1:0] = ‘00’ → CHx0 next
C[1:0] = ‘11’ → CHx1 next
R[1:0] = ‘01’ → register update R[1:0] = ‘11’ → no update
→ SR = ‘1’
C[1:0] = ‘00’ → CHx0 next
R[1:0] = ‘00’ → no update
BUSY
conversion n-1
of both CHxx
SDOA⁽¹⁾
A
D
x
16-bit data n - 2
CHAx
conversion n
of both CHx0
no conversion,
read access only
A
D
x
16-bit data n - 1
CHBx
A
D
A
16-bit data n
CHA0
conversion n + 1
of both CHx1
A _{16-bit data n}
D
B
CHB0
no conversion,
read access only
A
D
A
16-bit data n + 1
CHA1
SDOB⁽¹⁾
A
D
x
16-bit data n - 2
CHBx
High-Z
(1) ADS7263/7223 output data with the MSB located as ADS8363 and the last 2/4 bits being '0'.
Figure 36. Special Read Mode II Timing Diagram
(M0 = '0', M1 = '1', PDE = '0', SR = '1', CID = '0', Fully-Differential Example)
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Product Folder Link(s): ADS8363 ADS7263 ADS7223