ADS6143IRHB25 Datasheet, PDF (38/67 Pages) Texas Instruments – 14-BITS, 125/105/80/65 MSPS ADC WITH DDR LVDS/CMOS OUTPUTS

ADS6145, ADS6144
ADS6143, ADS6142
SLWS198B – JULY 2007 – REVISED MARCH 2008
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COMMON PLOTS
All plots are at 25°C, AVDD = DRVDD = 3.3 V, sine wave input clock, 1.5 V_PP differential clock amplitude, 50% clock duty
cycle, –1 dBFS differential analog input, internal reference mode, 0 dB gain, CMOS output interface (unless otherwise noted)
COMMON-MODE REJECTION RATIO vs FREQUENCY
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
0
50
100
150
200
250
300
f − Frequency − MHz
G077
Figure 85.
POWER DISSIPATION vs
SAMPLING FREQUENCY (DDR LVDS and CMOS)
0.8
f_IN = 2.5 MHz
0.7 _{CL = 5 pF}
0.6
0.5
LVDS
0.4
0.3
0.2
CMOS
0.1
0.0
0
25
50
75
100
f_S − Sampling Frequency − MSPS
Figure 86.
125
G078
DRVDD current vs
SAMPLING FREQUENCY ACROSS LOAD CAPACITANCE
(CMOS)
30
1.8 V, No Load
25
1.8 V, 5 pF
20
3.3 V, No Load
3.3 V, 5 pF
15
3.3 V, 10 pF
10
5
0
0
25
50
75
100
125
f_S − Sampling Frequency − MSPS
G079
Figure 87.
38
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