TSB82AA2B_14 Datasheet, PDF (37/102 Pages) Texas Instruments – OHCI-Lynx Controller

3.19 Power Management Capabilities Register
The power management capabilities register indicates the capabilities of the TSB82AA2B device related to PCI
power management. See Table 3−17 for a complete description of the register contents.
Type:
Offset:
Default:
Read/Update, Read only
46h
7E02h
Bit
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Default 0
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
Table 3−17. Power Management Capabilities Register Description
BIT
15
14−11
10
9
8−6
5
4
3
2−0
FIELD NAME
PME_D3COLD
PME_SUPPORT
D2_SUPPORT
D1_SUPPORT
AUX_CURRENT
DSI
RSVD
PME_CLK
PM_VERSION
TYPE
RU
R
R
R
R
R
R
R
R
DESCRIPTION
PCI_PME support from D3_cold. This bit can be set to 1 or cleared to 0 via bit 15 (PME_D3COLD) in
the miscellaneous configuration register at offset F0h in the PCI configuration space (see Section 3.23,
Miscellaneous Configuration Register). The miscellaneous configuration register is loaded from ROM.
When this bit is set to 1, it indicates that the TSB82AA2B device is capable of generating a PCI_PME
wake event from D3_cold. This bit state is dependent upon the TSB82AA2B V_AUX implementation and
may be configured by using bit 15 (PME_D3COLD) in the miscellaneous configuration register (see
Section 3.23).
PCI_PME support. This 4-bit field indicates the power states from which the TSB82AA2B device may
assert PCI_PME. This field returns a value of 1111b, indicating that PCI_PME may be asserted from
the D3_hot, D2, D1, and D0 power states.
Bit 14 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D3_hot
state.
Bit 13 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D2 state.
Bit 12 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D1 state.
Bit 11 contains the value 1 to indicate that the PCI_PME signal can be asserted from the D0 state.
D2 support. Bit 10 is hardwired to 1, indicating that the function supports the D2 device power state.
D1 support. Bit 9 is hardwired to 1, indicating that the TSB82AA2B device supports the D1 power state.
Auxiliary current. This 3-bit field reports the 3.3-V_AUX auxiliary current requirements. When bit 15
(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.
000b = Self powered
001b = 55 mA (3.3-V_AUX maximum current required)
Device-specific initialization. Bit 5 returns 0 when read, indicating that the TSB82AA2B device does
not require special initialization beyond the standard PCI configuration header before a generic class
driver is able to use it.
Reserved. Bit 4 returns 0 when read.
PME clock. Bit 3 returns 0 when read, indicating that no host bus clock is required for the TSB82AA2B
device to generate PCI_PME.
Power-management version. This field returns 010b when read, indicating that the TSB82AA2B
device is compatible with the registers described in the PCI Bus Power Management Interface
Specification (Revision 1.1).
3−14